參數(shù)資料
型號(hào)： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 26/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-53
Input Register
Timing Characteristics
Figure 3-26 Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
tISUE
50%
t
ISUD
t
IHD
50%
tICLKQ
1
0
tIHE
tIRECPRE
tIREMPRE
tIRECCLR
tIREMCLR
tIWCLR
tIWPRE
tIPRE2Q
tICLR2Q
tICKMPWH tICKMPWL
50%
Table 3-82 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tICLKQ
Clock-to-Q of the Input Data Register
0.63
0.71
0.84
1.01
ns
tISUD
Data Setup time for the Input Data Register
0.43
0.49
0.57
0.69
ns
tIHD
Data Hold time for the Input Data Register
0.00
ns
tISUE
Enable Setup time for the Input Data Register
0.43
0.49
0.57
0.69
ns
tIHE
Enable Hold time for the Input Data Register
0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.63
0.71
0.84
1.01
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.45
0.51
0.60
0.72
ns
tIREMCLR
Asynchronous Clear Removal time for the Input Data Register
0.00
ns
tIRECCLR
Asynchronous Clear Recovery time for the Input Data Register
0.22
0.25
0.30
0.36
ns
tIREMPRE
Asynchronous Preset Removal time for the Input Data Register
0.00
ns
tIRECPRE
Asynchronous Preset Recovery time for the Input Data Register
0.22
0.25
0.30
0.36
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data
Register
0.25
0.28
0.33
0.40
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data
Register
0.25
0.28
0.33
0.40
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.36
0.41
0.48
0.58
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.41
0.46
0.54
0.65
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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