參數資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數： 3/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
3- 32
Advanced v0.5
1.5 V LVCMOS (JESD8-11)
Low-voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5 V
applications. It uses 1.5 V input buffer and push-pull output buffer.
Table 3-37 Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V
Max, V
Min, V
Max, V
Min, V
mA
mA Max, mA1 Max, mA1
A2
2 mA
–0.3
0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
16
13
10
4 mA
–0.3
0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
4
33
25
10
6 mA
–0.3
0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
6
39
32
10
8 mA
–0.3
0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
8
55
66
10
12 mA
–0.3
0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI 12
12
55
66
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Figure 3-9
AC Loading
Table 3-38 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
0
1.5
0.75
–
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Test Point
Enable Path
Datapath
R to V
for t /t /t
CCI
LZ ZL
ZLS
35 pF for t
/t
/t /t
ZH ZHS
ZLS
ZL
5 pF for t
/t
HZ
LZ
R to GND for t
/t
HZ
ZH
ZHS
35 pF
R = 1 k
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