參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 45/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-71
Timing Characteristics
Table 3-94 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tAS
Address Setup time
0.30
0.34
0.40
0.48
ns
tAH
Address Hold time
0.00
ns
tENS
REN_B,WEN_B Setup time
0.20
0.22
0.26
0.32
ns
tENH
REN_B, WEN_B Hold time
0.03
0.04
0.05
ns
tBKS
BLK_B Setup time
0.29
0.33
0.39
0.47
ns
tBKH
BLK_B Hold time
0.00
ns
tDS
Input data (DI) Setup time
0.24
0.27
0.32
0.38
ns
tDH
Input data (DI) Hold time
0.00
ns
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
1.58
1.80
2.11
2.54
ns
Clock High to New Data Valid on DO (pass-through, WMODE = 1)
2.12
2.42
2.84
3.42
ns
tCKQ2
Clock HIGH to New Data Valid on DO (pipelined)
0.69
0.79
0.93
1.12
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (pass-through)
0.82
0.94
1.10
1.32
ns
RESET_B Low to Data Out Low on DO (pipelined)
0.82
0.94
1.10
1.32
ns
tREMRSTB
RESET_B Removal
0.31
0.35
0.41
0.49
ns
tRECRSTB
RESET_B Recovery
1.38
1.56
1.84
2.21
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.20
0.23
0.27
0.33
ns
tCYC
Clock Cycle time
1.96
2.22
2.61
3.14
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Table 3-95 RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tAS
Address Setup time
0.30
0.34
0.40
0.48
ns
tAH
Address Hold time
0.00
ns
tENS
REN_B,WEN_B Setup time
0.24
0.28
0.32
0.39
ns
tENH
REB_B, WEN_B Hold time
0.00
ns
tDS
Input data (DI) Setup time
0.22
0.25
0.30
0.36
ns
tDH
Input data (DI) Hold time
0.00
ns
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
1.93
2.19
2.58
3.10
ns
tCKQ2
Clock High to New Data Valid on DO (pipelined)
0.70
0.79
0.93
1.12
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (pass-through)
0.82
0.94
1.10
1.32
ns
RESET_B Low to Data Out Low on DO (pipelined)
0.82
0.94
1.10
1.32
ns
tREMRSTB
RESET_B Removal
0.31
0.35
0.41
0.49
ns
tRECRSTB
RESET_B Recovery
1.38
1.56
1.84
2.21
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.20
0.23
0.27
0.33
ns
tCYC
Clock Cycle time
1.96
2.22
2.61
3.14
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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