參數資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數： 14/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
3- 42
Advanced v0.5
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides
a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 3-62 Minimum and Maximum DC Input and Output Levels
SSTL2 Class I
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V
Min, V
Max, V
Min, V
mA
Max, mA1 Max, mA1
A2
15 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.54
VCCI - 0.62
15
87
83
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 3-17 AC Loading
Table 3-63 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.25
30
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Table 3-64 SSTL 2 Class I
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.25 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
–F
0.79
2.56
0.05
1.60
0.51
2.60
2.22
5.29
4.90
ns
Std.
0.66
2.13
0.04
1.33
0.43
2.17
1.85
4.40
4.08
ns
–1
0.56
1.81
0.04
1.14
0.36
1.84
1.57
3.74
3.47
ns
–2
0.49
1.59
0.03
1.00
0.32
1.62
1.38
3.29
3.05
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Test Point
30 pF
50
25
SSTL2
Class I
V
TT
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