參數(shù)資料
型號： M34524MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù)： 17/161頁
文件大?。?/td> 1199K
代理商： M34524MC-XXXFP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.2.00
Jul 27, 2004
page 113 of 159
REJ03B0091-0200Z
4524 Group
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
0010p5
p4
p3
p2
p1
p0
0p
13
–
Grouping:
Arithmetic operation
Operation:
(SP)
← (SP) + 1
(SK(SP))
← (PC)
(PCH)
← p
(PCL)
← (DR2–DR0, A3–A0)
(B)
← (ROM(PC))7–4
(A)
← (ROM(PC))3–0
(PC)
← (SK(SP))
(SP)
← (SP) – 1
TAD (Transfer data to Accumulator from register D)
0001010001
051
11
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Operation:
(A2–A0)
← (DR2–DR0)
(A3)
← 0
8
+p
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABPS (Transfer data to Accumulator and register B from PreScaler)
TABSI (Transfer data to Accumulator and register B from register SI)
1001111000
278
11
–
Grouping:
Serial I/O operation
Description: Transfers the high-order 4 bits (SI7–SI4) of
serial I/O register SI to register B, and
transfers the low-order 4 bits (SI3–SI0) of
serial I/O register SI to register A.
Operation:
(B)
← (SI7–SI4)
(A)
← (SI3–SI0)
1001110101
275
11
––
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (TPS7–
TPS4) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
Operation:
(B)
← (TPS7–TPS4)
(A)
← (TPS3–TPS0)
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0
are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by reg-
isters A and D in page p.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED.
When this instruction is executed, be careful not to over the stack because 1 stage of
stack register is used.
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