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參數(shù)資料
| 型號： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 126/161頁 |
| 文件大?。?/td> | 1199K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 67 of 159
REJ03B0091-0200Z
4524 Group
Table 21 Functions and states retained at power down
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Interrupt control registers V1, V2
Interrupt control registers I1 to I3
Selected oscillation circuit
Clock control register MR
Timer 1 to timer 4 functions
Timer 5 function
Timer LC function
Watchdog timer function
Timer control registers PA, W4
Timer control registers W1 to W3, W5, W6
Serial I/O function
Serial I/O control register J1
A/D function
A/D control registers Q1 to Q3
LCD display function
LCD control registers L1, L2
Voltage drop detection circuit
Port level
Pull-up control registers PU0, PU1
Key-on wakeup control registers K0 to K2
Port output format control registers
FR0 to FR3
External interrupt request flags
(EXF0, EXF1)
Timer interrupt request flags (T1F to T4F)
Timer interrupt request flag (T5F)
A/D conversion completion flag (ADF)
Serial I/O transmit/receive completion flag
SIOF
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
O
O
(Note 3)
O
(Note 3)
(Note 4)
O
O
O
(Note 5)
O
(Note 6)
(Note 7)
O
(Note 3)
O
(Note 4)
Notes 1:“O” represents that the function can be retained, and “” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at power
down, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at power down.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
go into the power down state.
5: LCD is turned off.
6: When the SVDE instruction is executed and “H” level is applied to
the VDCE pin, this function is valid at power down.
7: In the power down mode, C/CNTR1 pin outputs “L” level.
However, when the CNTR input is selected (W11, W10=“11”), C/
CNTR1 pin is in an input enabled state (output=high-impedance).
Other ports retain their respective output levels.
Power down mode
O
O
(Note 3)
O
(Note 4)
O
O
O
(Note 6)
(Note 7)
O
(Note 3)
O
(Note 4)
POWER DOWN FUNCTION
The 4524 Group has 2-type power down functions.
System enters into each power down state by executing the follow-
ing instructions.
Clock operating mode ...................... EPOF and POF instructions
RAM back-up mode ....................... EPOF and POF2 instructions
When the EPOF instruction is not executed before the POF or
POF2 instruction is executed, these instructions are equivalent to
the NOP instruction.
(1) Clock operating mode
The following functions and states are retained.
RAM
Reset circuit
XCIN–XCOUT oscillation
LCD display
Timer 5
(2) RAM back-up mode
The following functions and states are retained.
RAM
Reset circuit
(3) Warm start condition
The system returns from the power down state when;
External wakeup signal is input
Timer 5 underflow occurs
in the power down mode.
In either case, the CPU starts executing the program from address
0 in page 0. In this case, the P flag is “1.”
(4) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
reset pulse is input to RESET pin,
reset by watchdog timer is performed, or
reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state of
the power down flag (P) with the SNZP instruction. The warm start
condition from the clock operating mode can be identified by exam-
ining the state of T5F flag.
Clock
operating
RAM
back-up
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