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參數(shù)資料
| 型號： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 137/161頁 |
| 文件大小： | 1199K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 77 of 159
REJ03B0091-0200Z
4524 Group
D9/INT1 pin
Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in program, be careful about the following notes.
Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 68)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
68).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 68).
LA
4
; (02)
TV1A
; The SNZ1 instruction is valid ...........
LA
8
; (12)
TI2A
; Control of INT1 pin input is changed
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 68 External 1 interrupt program example-1
Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared, the power down function
is selected and the input of INT1 pin is disabled, be careful about
the following notes.
When the input of INT1 pin is disabled, invalidate the key-on
wakeup function of INT1 pin (register K22 = “0”) before system
goes into the power down mode. (refer to Figure 69).
LA
0
; (02)
TK2A
; INT1 key-on wakeup invalid ...........
DI
EPOF
POF2
; RAM back-up
: these bits are not used here.
Fig. 69 External 1 interrupt program example-2
Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in program, be careful about the fol-
lowing notes.
Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 70)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
70).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 70).
LA
4
; (02)
TV1A
; The SNZ1 instruction is valid ...........
LA
12
; (12)
TI2A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 70 External 1 interrupt program example-3
17
A/D converter-1
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conver-
sion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the com-
parator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
LA
8
; (02)
TV2A
; The SNZAD instruction is valid ........
LA
0
; (02)
TQ1A
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
SNZAD
NOP
: these bits are not used here.
Fig. 71 A/D converter program example-3
18
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