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參數(shù)資料
| 型號(hào)： | M34524MC-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 115/161頁(yè) |
| 文件大?。?/td> | 1199K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 57 of 159
REJ03B0091-0200Z
4524 Group
LCD FUNCTION
The 4524 Group has an LCD (Liquid Crystal Display) controller/
driver. When the proper voltage is applied to LCD power supply in-
put pins (VLC1–VLC3) and data are set in timer control register
(W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the
LCD controller/driver automatically reads the display data and con-
trols the LCD display by setting duty and bias.
4 common signal output pins and 20 segment signal output pins
can be used to drive the LCD. By using these pins, up to 80 seg-
ments (when 1/4 duty and 1/3 bias are selected) can be controlled
to display. The LCD power input pins (VLC1–VLC3) are also used as
pins SEG0–SEG2. When SEG0–SEG2. The internal power (VDD) is
used for the LCD power.
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select the
proper display method for the LCD panel being used.
1/2 duty, 1/2 bias
1/3 duty, 1/3 bias
1/4 duty, 1/3 bias
Table 17 Duty and maximum number of displayed pixels
(2) LCD clock control
The LCD clock is determined by the timer LC count source selec-
tion bit (W62), timer LC control bit (W63), and timer LC.
Accordingly, the LCD clock frequency (F) is obtained by the follow-
ing formula. Numbers ( to ) shown below the formula
correspond to numbers in Figure 42, respectively.
When using the prescaler output (ORCLK) as timer LC count
source (W62=“1”)
F = ORCLK
When using the bit 4 of timer 5 as timer LC count source (W62=“0”)
F =
T54
[LC: 0 to 15]
The frame frequency and frame period for each display method
can be obtained by the following formula:
Frame frequency =
(Hz)
Frame period =
(s)
F: LCD clock frequency
1/n: Duty
Fig. 42 LCD clock control circuit structure
Duty
1/2
1/3
1/4
Used COM pins
COM0, COM1 (Note)
COM0–COM2 (Note)
COM0–COM3
Maximum number of displayed pixels
40 segments
60 segments
80 segments
Note: Leave unused COM pins open.
1
LC + 1
1
2
1
LC + 1
F
n
F
Note: Count source is stopped by setting “0” to this bit.
Timer LC
1/2
W63
0
1
(Note)
T54
W62
0
1
ORCLK
LCD clock
(4)
Reload register RLC
(4)
Register A
(TLCA)
1
2
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