參數(shù)資料
型號: M34524MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 14/161頁
文件大?。?/td> 1199K
代理商: M34524MC-XXXFP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.2.00
Jul 27, 2004
page 110 of 159
REJ03B0091-0200Z
4524 Group
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
1000110001
231
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 re-
load register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
Operation:
(T27–T24)
← (B)
(R27–R24)
← (B)
(T23–T20)
← (A)
(R23–R20)
← (A)
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B)
T4HAB (Transfer data to register R4H from Accumulator and register B)
1000110010
232
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 3 and timer 3 re-
load register R3. Transfers the contents of
register A to the low-order 4 bits of timer 3
and timer 3 reload register R3.
Operation:
(T37–T34)
← (B)
(R37–R34)
← (B)
(T33–T30)
← (A)
(R33–R30)
← (A)
1000110011
233
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 re-
load register R4L. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4L.
Operation:
(T47–T44)
← (B)
(R4L7–R4L4)
← (B)
(T43–T40)
← (A)
(R4L3–R4L0)
← (A)
1000110111
237
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 re-
load register R4H. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4H.
Operation:
(R4H7–R4H4)
← (B)
(R4H3–R4H0)
← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
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