Rev.2.00
Jul 27, 2004
page 69 of 159
REJ03B0091-0200Z
4524 Group
Fig. 55 State transition
Fig. 56 Set source and clear source of the P flag
Fig. 57 Start condition identified example using the SNZP instruction
S
R
Q
Power down flag P
POF or
POF2
instruction
Reset input
q Set source
q Clear source
Reset input
EPOF instruction +
POF or
POF2
instruction
EPOF instruction +
Program start
P = “1”
?
Yes
Warm start
Cold start
No
T5F = “1”
?
Yes
No
Return from
timer 5 underflow
Return from
external wakeup signal
Reset
B
Operation state
Operation source clock: f(XIN)
Oscillation circuit:
Ceramic resonator
On-chip oscillator: Stop
RC oscillation circuit: Stop
A
C
E
Clock operating mode
Main clock: stop
Sub-clock: operating
Wakeup
(Stabilizing time c )
POF2 instruction
execution
F
RAM back-up mode
POF2 instruction
execution
High-speed mode
D
Operation clock: f(XCIN)
Oscillation circuit:
Quartz-crystal oscillation
MR0
←0
(Note 4)
MR0
←1
(Note 4)
Low-speed
mode
Wakeup
(Stabilizing time b )
POF2 instruction
execution
Wakeup
(Stabilizing time d )
POF2 instruction
execution
Wakeup
(Stabilizing time e )
POF instruction
execution
Wakeup
(Stabilizing time e )
POF instruction
execution
Wakeup
(Stabilizing time d )
POF instruction
execution
Wakeup
(Stabilizing time b )
(Stabilizing time a )
POF instruction
execution
Wakeup
(Stabilizing time c )
Main clock: stop
Sub-clock: stop
CMCK instruction
execution (Note 3)
Operation state
Operation source clock:
f(RING)
Oscillation circuit:
On-chip oscillator
Ceramic resonator:
Operating (Note 2)
RC oscillation circuit: Stop
CRCK instruction
execution (Note 3)
Operation state
Operation source clock: f(XIN)
Oscillation circuit:
RC oscillation
On-chip oscillator: Stop
Ceramic resontor: Stop
Operation state
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times.
Stabilizing time b : In high-speed through-mode, microcomputer starts its operation after counting the f(RING) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(RING) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(RING) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(RING) 5400 times.
Stabilizing time c : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 5400 times.
Stabilizing time d : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 21 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 42 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 84 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 168 times.
Stabilizing time e : In low-speed through-mode, microcomputer starts its operation after counting the f(XCIN) 675 times.
In low-speed/2 mode, microcomputer starts its operation after counting the f(XCIN) 1350 times.
In low-speed/4 mode, microcomputer starts its operation after counting the f(XCIN) 2700 times.
In low-speed/8 mode, microcomputer starts its operation after counting the f(XCIN) 5400 times.
Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock.
3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped.
4: The main clock (f(XIN) or f(RING)) or sub-clock (f(XCIN)) is selected for operation source clock by the bit 0 of clock control register MR.
5: The sub-clock (quartz-crystal oscillation) is operating except in state F.
T5F