8-20
Specifications
8.6.2 PQFP Package Pin Summary
Table 8.20
lists the L80600 pins in numerical order.
Table 8.20
Signal
PQFP Package Pin Assignments
Pin
Signal
Pin
RESERVE_GND
IO_VDD
IO_VSS
LED_10/10_
ADV/SPEED [1]
LED_100/100_
ADV
CORE_VDD
CORE_VSS
LED_1000/
1000FDX_ADV
LED_DUPLEX/
1000HDX_ADV
TEST
IO_VDD
IO_VSS
SDA
SCL
MANUAL_M/
S_ ADVERTISE
AN_EN/TX_
TCLK
IO_VDD
IO_VSS
MANUAL_M/
S_ENABLE
NC_MODE
CORE_VDD
CORE_VSS
CORE_SUB
LED_ACT
/PHYAD_0
LED_COL
/PHYAD_1
IO_VDD
IO_VSS
LED_LNK
/PHYAD_2
LED_TX/
PHYAD_3
TEST
LED_RX/PHY
AD_4
SPEED [0]/PORT_
TYPE/INT
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal
Pin
RA_ASUB
RA_AVDD
RA_AGND
RXDA+
RXDA-
RA_AVDD
RA_AGND
CDA_AVDD
TXDA+
TXDA-
CDA_AGND
CDB_AGND
TXDB-
TXDB+
CDB_AVDD
RB_AGND
RB_AVDD
RXDB-
RXDB+
RB_AGND
RB_AVDD
RB_ASUB
BG_AVDD
BG_REF
BG_AGND
BG_SUB
PGM_AVDD
PGM_AGND
SHR_VDD
SHR_GND
RC_ASUB
RC_AVDD
RC_AGND
RXDC+
RXDC-
RC_AVDD
RC_AGND
CDC_AVDD
TXDC+
TXDC-
CDC_AGND
CDD_AGND
TXDD-
TXDD+
CDD_AVDD
RD_AGND
RD_AVDD
RXDD-
RXDD+
RD_AGND
RD_AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
RD_ASUB
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
CORE_SUB
CORE_VSS
CORE_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
CORE_VSS
CORE_VDD
RESERVE_
FLOAT
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
CORE_SUB
CORE_VSS
CORE_VDD
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
RESERVE_
FLOAT
SI
SO
RESERVE_
FLOAT
RESERVE_
FLOAT
IO_VSS
IO_VDD
COL
CRS
RX_ER
RX_DV
RXD7
RXD6
IO_VSS
IO_VDD
RXD5
RXD4
RXD3
RXD2
IO_VSS
IO_VDD
RXD1
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
RXD0
RX_CLK
CORE_SUB
CORE_VSS
CORE_VDD
TX_CLK
IO_VSS
IO_VDD
TX_ER
TX_EN
TXD7
CORE_VSS
CORE_VDD
TXD6
TXD5
TXD4
TXD3
IO_VSS
IO_VDD
TXD2
TXD1
TXD0
GTX_CLK
IO_VSS
IO_VDD
MDIO
MDC
OSC_VSS
REF_CLK
REF_SEL
OSC_VDD
TRST
TDI
TDO
TMS
CORE_VDD
CORE_VSS
CORE_SUB
TCK
RESET
RESERVE_GND
RESERVE_GND
IO_VDD
IO_VSS
RESERVE_GND
RESERVE_GND
CORE_VDD
CORE_VSS
CORE_SUB
RESERVE_GND
RESERVE_GND
RESERVE_GND
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Signal
Pin
Signal
Pin