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參數(shù)資料
| 型號(hào)： | L80600 |
| 英文描述： | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| 中文描述： | L80600 10/100/1000 Mbits /秒以太網(wǎng)PHY技術(shù)手冊(cè)3月1日 |
| 文件頁(yè)數(shù)： | 114/192頁(yè) |
| 文件大?。?/td> | 1344K |
| 代理商： | L80600 |
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5-16
Configuration Options
The interrupt signal’s polarity can be programmed in the ICTR register.
The polarity can be configured active-HIGH or active-LOW. In the latched
mode, the interrupt signal is asserted and remains asserted while the
corresponding enabled status bit is asserted. The status bits are the
sources of the interrupt. These bits are mapped in the ISR. When the
interrupt status bit is 1, the interrupt signal is asserted if the
corresponding IER bit is enabled. An interrupt status bit can be cleared
by writing a 1 to the corresponding bit in the ICLR. The clear bit returns
to 0 automatically after the interrupt status bit is cleared.
The RRR register contains the current status of the signals being
monitored. Note that the status of the configuration, duplex, and speed
are recorded in the most recent period while the link was up.
The IRR records the
reason
that an interrupt status bit is asserted. For
example, if the ISR_LINK bit is asserted in the ISR because a link is
achieved, a 1 is stored in the corresponding IRR bit field. This IRR bit
field is not changed until the interrupt is serviced, regardless of how
many times the source status (in RRR) changes in the intervening
period. The IRR bit can be cleared by writing a 1 to the corresponding
bit in the ICLR register.
The purpose of the IRR is for the interrupt logic to determine the next
state change to cause an interrupt. In reality, the PHY may operate at a
much faster pace than the interrupt service provider. The IRR provides a
mechanism for the higher layers to decipher the context of the interrupt
although the context of the system may have changed by the time the
interrupt is serviced. For instance, when a link is lost and regained in
quick succession, it is likely that a sequence of interrupts are generated
by the same event. The IRR preserves the status of the event that may
have changed during the interrupt service. A new interrupt may be
generated if the status is changed based on the comparison between the
IRR and the RRR.
Note:
All the interrupt registers are extended registers located in
the expanded memory space. Please refer to
Chapter 4,
“Registers”
for details.
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