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參數(shù)資料
| 型號(hào)： | L80600 |
| 英文描述： | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| 中文描述： | L80600 10/100/1000 Mbits /秒以太網(wǎng)PHY技術(shù)手冊(cè)3月1日 |
| 文件頁(yè)數(shù)： | 125/192頁(yè) |
| 文件大?。?/td> | 1344K |
| 代理商： | L80600 |
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LED/Strapping Options
6-11
6.5 LED/Strapping Options
The five PHY address inputs pins are shared with the LED pins as shown
below.
The L80600 can be set to respond to any of 32 possible PHY addresses.
However, PHY Address 0 puts the L80600 in power-down/isolate mode.
When in power-down/isolate mode, the device turns off its transmitter,
receiver, and GMII inputs/outputs. When in this mode, the part only
responds to MDIO/MDC activity. After power-on, the PHY should be
taken out of power-down isolation by resetting bit 11 of register 0x00.
Each L80600 or port sharing an MDIO bus in a system must have a
unique physical address.
The pull-up or pull-down state of each of the PHYAD inputs is latched
(register 0x10) at system power-up or reset. For further details relating
to the latch-in timing requirements of the PHY Address pins, as well as
the other hardware configuration pins, refer to the RESETn timing in
Section 8.5.6, “Reset Timing,” page 8-16
.
Because the PHYAD strap options share the LED output pins, the
external components required for strapping and LED usage must be
considered in order to avoid contention.
Specifically, when the LED outputs are used to drive LEDs directly, the
active state of each output driver is dependent on the logic level sampled
by the corresponding PHYAD input upon power-up/reset. For example, if
a given PHYAD input is resistively pulled LOW, the corresponding output
is then configured as an active-HIGH driver. Conversely, if a given
Table 6.6
PHY Address Mapping
Pin
PHYAD Function
LED Function
200
PHYAD_0
ACT
201
PHYAD_1
COL
204
PHYAD_2
LNK
205
PHYAD_3
TX
207
PHYAD_4
RX
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