![](http://datasheet.mmic.net.cn/270000/L80223_datasheet_16027354/L80223_46.png)
Draft 6/5/00
2-26
Functional Description
Copyright 2000 by LSI Logic Corporation. All rights reserved.
are detected during any 10
μ
s interval. When a loss of data is detected,
the receive squelch is turned on again.
2.2.8.4 Squelch (10 Mbits/s)
The TP squelch algorithm for 10 Mbits/s mode is identical to the
100 Mbits/s mode, except:
The 10 Mbits/s TP squelch algorithm is not used for link integrity, but
to sense the beginning of a packet
The receiver goes into the unsquelch state if the input voltage
exceeds the squelch levels for three bit times with alternating polarity
within a 50 to 250 ns interval
The receiver goes into the squelch state when SOI is detected
Unsquelch detection has no effect on link integrity (link pulses are
used in 10 Mbits/s mode for that purpose)
Start of packet is determined when the receiver goes into the
unsquelch state and CRS is asserted
The receiver meets the squelch requirements defined in IEEE 802.3
Clause 14.
2.2.8.5 Equalizer Disable
Setting the Equalizer Disable bit (EQLZR) in the MI serial port
Configuration 1 register disables the adaptive equalizer. When disabled,
the equalizer is forced into the response it would normally have if zero
cable length was detected.
2.2.8.6 Receive Level Adjust
Setting the Receive Level Adjust bit (RLV0) in the MI serial port
Configuration 1 register lowers the receiver squelch and unsquelch levels
by 4.5 dB. Setting this bit may allow the device to support longer cable
lengths.
2.2.8.7 Receive Activity Indication
Appropriately setting the programmable LED output select bits in the MI
serial port LED Configuration 2 register programs receive activity to
appear on some of the PLED[5:0]n pins. When one or more of the