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參數(shù)資料
| 型號(hào)： | L80223 |
| 廠商： | LSI CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX/FX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁(yè)數(shù)： | 183/192頁(yè) |
| 文件大小： | 1306K |
| 代理商： | L80223 |
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Draft 6/5/00
Repeater Applications
A-23
Copyright 2000 by LSI Logic Corporation. All rights reserved.
Because the FBI is a 5-bit interface, it requires that the 4B5B
encoder/decoder be bypassed. The FBI is automatically selected on the
L80223 when the 4B5B encoder/decoder is bypassed. To bypass the
4B5B encoder/decoder, set the BYP_ENC bit in the MI serial port
Configuration 1 register. Some applications may also require the
scrambler/descrambler to be bypassed. To bypass the
scrambler/descrambler, set the BYP_SCR bit in the MI serial port
Configuration 1 register.
For most repeaters, it is necessary to disable the internal CRS loopback.
To do this, set the TX_EN to CRS loopback disable bit (TXEN_CRS) in
the MI serial port Configuration 1 register.
For some particular types of repeaters, it may be desirable to either
enable or disable AutoNegotiation, force Half Duplex operation, and
enable either 100 Mbits/s or 10 Mbits/s operation. To configure any of
these modes, set the appropriate bits in the MI serial port Control
register.
The FBI requires 16 signals between the L80223 and a repeater core.
The FBI signal count to a repeater core is be 16 multiplied by the number
of ports, which can be quite large. The signal count between the L80223
and repeater core can be reduced by 8 per device if the receive output
pins are shared and RX_EN is used to enable only that port where CRS
is asserted. Refer to
Section A.9, “MII Controller Interface,” page A-15
for
more details about using the RX_EN pin.
A.14.3 Clocks
Normally, transmit data over the MII is clocked into the L80223 on the
edge of the transmit output clock (TX_CLK). It may be desirable or
necessary in some repeater applications to clock in the transmit data
from a master clock generated at the repeater core. This requires that
transmit data (TXD[3:0]) be clocked into the device on edges of the
OSCIN input clock.
Notice from the timing diagrams that OSCIN generates TX_CLK, and
TXD[3:0] data is clocked into the L80223 on TX_CLK edges. This means
that TXD data is also clocked in on OSCIN edges as well. Thus, an
external clock driving the OSCIN input can also be used as the clock for
TXD[3:0].
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L80600 | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| L811-1X1T-03 | 1port.None LEDs.low profile RJ45 10/100Base-TX |
| L82-510 | Logic IC |
| L82-511 | Logic IC |
| L82-512 | Logic IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80223/A | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/C | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/D | 制造商:LSI Corporation 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| L80223/D-E6 | 制造商:LSI Corporation 功能描述:TRANSITION TO P/N 68032B1 - Bulk |
| L80223/D-LEADFREE | 制造商:LSI Corporation 功能描述: |
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