Draft 6/5/00
Block Diagram Description
2-17
Copyright 2000 by LSI Logic Corporation. All rights reserved.
interface. To do this, it decodes the data and strips off the SOI pulse.
Because the Clock and Data Recovery block has already separated the
clock and data from the TP receiver, that block inherently performs the
the Manchester decoding.
2.2.4.3 Decoder Bypass
Setting the Bypass Encoder/Decoder bit (BYP_ENC) in the MI serial port
Configuration 1 register bypasses the 4B5B decoder. When this bit is set,
5B code words are passed directly to the controller interface from the
descrambler without any of the alterations described in
Section 2.2.4,
“Decoder,” page 2-16
. Additionally, the CRS pin is continuously asserted
whenever the device is in the Link Pass state. Setting the bit
automatically places the device in the FBI mode as described in the
subsection entitled “FBI Selection”
on
page 2-13
.
2.2.5 Scrambler
100BASE-TX transmission requires scrambling to reduce the radiated
emissions on the twisted pair. The scrambler takes the NRZI encoded
data from the 4B5B encoder, scrambles it per the IEEE 802.3
specifications, and sends it to the TP transmitter. A scrambler is not used
for 10 Mbits/s operation.
2.2.5.1 Scrambler Bypass
Setting the Bypass Encoder/Decoder bit (BYP_SCR) in the MI serial port
Configuration 1 register bypasses the scrambler. When this bit is set, 5B
data bypasses the scrambler and goes directly to the 100BASE-TX
transmitter.
2.2.6 Descrambler
The descrambler block shown in
Figure 2.1
is used in 100BASE-TX
operation. The device descrambler takes the scrambled NRZI data from
the data recovery block, descrambles it according to IEEE 802.3
specifications, aligns the data on the correct 5B word boundaries, and
sends it to the 4B5B decoder.
The algorithm for synchronization of the descrambler is the same as the
algorithm outlined in the IEEE 802.3 specification.