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參數(shù)資料
| 型號： | IDTSSTE32882KA1AKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 35/75頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標準包裝： | 170 |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應商設備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 托盤 |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
40
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1 Device Initialization Sequence1 when Power and Clock are Stable
1. x=Logic low or lolgic high. Z=floating.
2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
3. The feedback clock (FBOUT and FBOUT) pins may or may not be actively driven by the device.
4. QxCKEn and ERROUT will be driven to these logic states by the register after RESET is driven low and VDD is nominal.
5. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge, within (tSTAB - tACT)
us, the state of QxODTx is a function of DODTx (high or low)
Parity
The SSTE32882KA1 includes a parity checking function. The SSTE32882KA1 accepts a parity bit from the memory
controller at its input pin PAR_IN one cycle after the corresponding data input, compares it with the data received on the
D-inputs and indicates on its open-drain ERROUT pin (active low) whether a parity error has occurred. The computation only
takes place for data which is qualified by at least one of the DCS[n:0] signals being LOW.
If an error occurs, and ERROUT is driven low with the third input clock edge after the corresponding data on the D-inputs. It
becomes high impedance with the 5th input clock cycle after the data corresponding with a parity error. In case of consecutive
errors ERROUT becomes high impedance with the 5th input clock cycle after the last data corresponding with a parity error.
The DIMM-dependent signals (DCKE0, DCKE1, DCS0, DCS1, DODT0 and DODT1) are not included in the parity check
computations.
Parity Timing Scheme Waveforms
The PAR_IN signal arrives one input clock cycle after the corresponding data input signals. ERROUT is generated three input
clock cycles after the corresponding data is registered. If ERROUTgoes low, it stays low for a minimum of two input clock
cycles or until RESET is driven low. The following figure shows the parity diagram with single parity-error occurrence and
assumes the occurrence of only one parity error when data is clocked in at the n input clock cycle (PAR_IN clocked in on the
n+1 input clock cycle).
Step Power
Inputs: Signals provided by the controller
Outputs: Signals provided by the device
VDD,
AVDD,
PVDD
RESET
Vref
DCS
[n:1]2
DODT
[0:1]
DCKE
[0:1]
DA/C
PAR_IN CK, CK
QCS
[0:1]
QODT
[0:1]
QCKE
[0:1]
QxA/C
ERROUT
Y[0:3]
FB
OUT3
0
VDD
H
stable
voltage
X
running
X
running running
1
VDD
H
stable
voltage
X
running
X
running running
2
VDD
L
stable
voltage
X
running
Z
L4
Z
H4
ZZ
3
VDD
L
stable
voltage
X
running
ZZ
LZ
HZ
Z
4
VDD
L
stable
voltage
H
X
L
X
running
Z
LZ
HZ
Z
5
VDD
L
stable
voltage
HX
L
XX
running
Z
LZ
HZ
Z
6
VDD
H
stable
voltage
HX
L
XX
running
H
L5
LX
H
running running
7
VDD
H
stable
voltage
H
X
running
After Step 6 (Step 7 and beyond), the device outputs are as defined
in the device Function Tables.
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