參數(shù)資料
型號: IDTSSTE32882KA1AKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/75頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標準包裝: 170
類型: 時鐘緩沖器/驅(qū)動器,多路復用器
PLL:
主要目的: 存儲器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 托盤
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
22
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Timing Requirements
Symbol
Parameter
Conditions
DDR3/DDR3L-
800/ 1066/1333
DDR3/DDR3L
-1600
DDR3-1866
Unit
Min
Max
Min
Max
Min
Max
fCLOCK
Input Clock Frequency
Application Frequency1
1
All specified timing parameters apply.
300
670
300
810
300
945
MHz
fTEST
Input Clock Frequency
Test Frequency2
2
Timing parameters specified for frequency band 2 apply.
70
300
70
300
70
300
MHz
tCH/tCL
Pulse Duration, CK, CK
HIGH or LOW
0.4
tCK3
3
Clock cycle time.
tACT
Inputs active time before
RESET is taken HIGH4
4
This parameter is not necessarily production tested (see the “Voltage Waveforms for Setup and Hold Times–Hold Time
Calculation”figure below).
DCKE0/1 = LOW and
DCS[n:0] = HIGH
88
8
tCK3
tMRD
Command word to
command word
programming delay
Number of clock cycles
between two command
programming accesses
88
8
tCK3
tINDIS
Input Buffers disable time
after DCKE[1:0] is LOW
DCKE[1:0] = LOW;
RESET = HIGH; CK/CK =
Toggling; RC9[DBA1] = 1
and RC9[DBA0] = 0 or 1
1
4
14
tCK3
tQDIS
Output Buffers Hi-Z after
QxCKEn is driven LOW
DCKE[1:0] = LOW;
RESET = HIGH; CK/CK =
Toggling; RC9[DBA1] = 1
and RC9[DBA0] = 0 or 1
1.5
tCK3
tCKOFF
Number of tCK required for
both DCKE0 and DCKE1
to remain LOW before both
CK/CK are driven low
DCKE[1:0] = LOW;
RESET = HIGH;
CK/CK = Toggling
55
5
tCK3
tCKEV
Input buffers (DCKE0 and
DCKE1) disable time after
CK/CK = LOW
DCKE[1:0] = LOW;
RESET = HIGH;
CK/CK = LOW
22
2
tCK3
tFixedout
puts
Static Register Output after
DCKE0 or DCKE1 is
HIGH at the input (exit
from Power Saving state)
RC9[DBA1] = 1 and
RC9[DBA0] = 0 or 1
1
3
14
tCK3
tSU
Setup Time5
Input valid before CK/CK
100
50
40
ps
tH
Hold Time6
Input to remain valid after
CK/CK
175
125
75
ps
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