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參數(shù)資料
| 型號(hào)： | IDTSSTE32882KA1AKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 26/75頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標(biāo)準(zhǔn)包裝： | 170 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 托盤 |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
32
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn) Skew”). This
parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left side clock pairs between
Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested parameter and has to be considered
as a design goal only.
2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based on tPW.
4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential output
clock that will be used to sample the same C/A data. tSTAOFF may vary by the amount of tDYNOFF based on voltage and temperature drift as
well as tracking error and jitter. Including this variation tSTAOFF may not exceed the limits set by tSTAOFF(MIN) and tSTAOFF(MAX).
6. See “Measurement Requirement for tSTAOFF and tDYNOFF“.
7. Implies a -3 dB bandwidth and jitter peaking of 3 dB.
tDYNOFF6
Maximum variation in
delay between the input
& output clock
-
160
-
130
-
110
-
90
-
70
ps
SSC modulation
frequency
30
33
30
33
30
33
30
33
30
33
kHz
SSC clock input
frequency deviation
0.00
-0.5
0.00
-0.5
0.00
-0.5
0.00
-0.5
0.00
-0.5
%
tBAND
PLL Loop bandwidth
(-3 dB from unity gain)
257
307
357
407
-457
-MHz
Symbol
Parameter
Conditions
DDR3/
DDR3-800
DDR3/
DDR3L-1066
DDR3/
DDR3L-1333
DDR3/
DDR3L-1600
DDR3-1866
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTSSTE32882KA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTUB32866BHLF | 功能描述:IC BUFFER 25BIT CONF REG 96LFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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