- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2000 > IDTSSTE32882KA1AKG (IDT, Integrated Device Technology Inc)IC REGISTERING CLK DRIVER 176BGA PDF資料下載
參數(shù)資料
| 型號： | IDTSSTE32882KA1AKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 31/75頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標準包裝： | 170 |
| 類型： | 時鐘緩沖器/驅動器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應商設備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
37
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Initialization
The SSTE32882KA1 can be powered-on at 1.5V, 1.35V or 1.25V. After the voltage transition, stable power is provided for a
minimum of 200 s with RESET asserted.
When the reset input (RESET) is low, all input receivers are disabled, and can be left floating. The RESET input is referenced
to VDD/2, therefore the reference voltage (VREF) is not required to be stable during reset. In addition, when RESET is low, all
control registers are restored to their default states. The QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs must drive low
during reset, and all other outputs must float. As long as the RESET input is pulled low the register is in low power state and
input termination is not present.
A certain period of time (tACT) before the RESET input is pulled high the reference voltage needs to be stable within
specification, the clock input signal must be stable, the register inputs DCS[n:0] must be pulled high to prevent any accidental
access to the control registers. Also, DCKE0 and DCKE1 inputs must be pulled low for the complete stabilization time (tSTAB).
After reset and after the stabilization time (tSTAB), the register must meet the input setup and hold specification before
accepting and transfering data from the register inputs to the register outputs. The RESET input must always be held at a valid
logic level once the input clock is present.
To ensure defined outputs from the register before a stable clock has been supplied, the register must enter the reset state during
power-up. It may leave this state only after a low to high transition on RESET while a stable clock signal is present on CK and
CK.
In the DDR3 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore,
no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs
will float quickly (except for QACKE0, QACKE1, QBCKE0 and QBCKE1, which are driven low), relative to the time to
disable the differential input receivers. The figure below shows the system timing of clock and data during the initialization
sequence.
Timing of clock and data during initialization sequence
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
4 QxCKEn, QxODTn, QxCSn are not included in this range.
CK(1)
VDD
DCKE[0:1]
RESET
DA/C(2)
DODT[0:1]
DCS0
DCS[n:1](4)
PLL lock 6
μs
tACT = 8 cycles
tINIT = 200 μs
Controller guarantees high logic
Controller guarantees valid logic
Controller guarantees low logic
Controller guarantees valid logic
Register proper function and timing starting from here
Register drives CKE low until ready to transfer input signals
QxCKE[0:1]
QxODT[0:1]
QxCS[n:0](4)
ERROUT
Step 0,1 Step 2
Step 3
Step 5
Step 6
Step 7
Step 4
QxA/C(3)
High or Low
Y[0:3](1)
Register guarantees low logic
Register guarantees high logic
相關PDF資料 |
PDF描述 |
|---|---|
| ISD1750SYR | IC VOICE REC/PLAY 50SEC 28-SOIC |
| ISD5008EYI | IC VOICE REC/PLAY 4-8MIN 28-TSOP |
| ISL12008IB8Z | IC RTC I2C LO-POWER 8-SOIC |
| ISL12020MIRZ-T7A | IC RTC/CALENDAR TEMP SNSR 20DFN |
| ISL12022IBZ-T7A | IC RTC/CALENDAR TEMP SNSR 8SOIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDTSSTE32882KA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTUB32866BHLF | 功能描述:IC BUFFER 25BIT CONF REG 96LFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| IDTSSTUB32S869AHLF | 功能描述:IC REGISTERED BUFFER 150-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 信號緩沖器，中繼器，分配器 系列:- 標準包裝:160 系列:- 類型:轉發(fā)器 Tx/Rx類型:以太網(wǎng) 延遲時間:- 電容 - 輸入:- 電源電壓:2.37 V ~ 2.63 V 電流 - 電源:60mA 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:托盤 其它名稱:Q5134101 |
| IDTSSTUB32S869AHLFT | 功能描述:IC REGISTERED BUFFER 150-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 信號緩沖器，中繼器，分配器 系列:- 標準包裝:160 系列:- 類型:轉發(fā)器 Tx/Rx類型:以太網(wǎng) 延遲時間:- 電容 - 輸入:- 電源電壓:2.37 V ~ 2.63 V 電流 - 電源:60mA 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:托盤 其它名稱:Q5134101 |
| IDTSSTVF16857AGLF | 功能描述:IC DDR REGISTER 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
發(fā)布緊急采購，3分鐘左右您將得到回復。