參數(shù)資料
型號： HYB18T512160AF
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 97/117頁
文件大?。?/td> 2102K
代理商： HYB18T512160AF
Data Sheet
97
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
7
Electrical Characteristics
7.1
Speed Grade Defenitions
Table 51
Speed Grade
IFX Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Speed Grade Definition Speed Bins for DDR667
DDR2–667C
–3
4–4–4
Min.
5
3
3
45
57
12
12
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
Unit
Note
t
CK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
Max.
8
8
8
70000
—
—
—
Max.
8
8
8
70000
—
—
—
@ CL = 3
@ CL = 4
@ CL = 5
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is
recognized as low.
4) The output timing reference voltage level is
V
TT
. See section 8 for the reference load for timing measurements.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Table 52
Speed Grade
IFX Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Speed Grade Definition Speed Bins for DDR533 and DDR400
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
Unit
Note
t
CK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
Max.
8
8
8
70000
—
—
—
Max.
8
8
8
70000
—
—
—
@ CL = 3
@ CL = 4
@ CL = 5
1)2)3)4)
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3 512-Mbit DDR2 SDRAM
HYB18T512160AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
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HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
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