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參數(shù)資料
| 型號： | HYB18T512160AF |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 45/117頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512160AF |
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Data Sheet
45
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.14
Bank Activate Command
The Bank Activate command is issued by holding CAS
and WE HIGH with CS and RAS LOW at the rising edge
of the clock. The bank addresses BA[1:0] are used to
select the desired bank. The row addresses A0 through
A13 are used to determine which row to activate in the
selected bank for
×
4 and
×
8 organized components.
For
×
16 components row addresses A0 through A12
have to be applied. The Bank Activate command must
be applied before any Read or Write operation can be
executed. Immediately after the bank active command,
the DDR2 SDRAM can accept a read or write command
(with or without Auto-Precharge) on the following clock
cycle. If a R/W command is issued to a bank that has
not satisfied the
t
RCD.MIN
specification, then additive
latency must be programmed into the device to delay
the R/W command which is internally issued to the
device. The additive latency value must be chosen to
assure
t
RCD.MIN
is satisfied. Additive latencies of 0, 1, 2,
3, 4 and 5 are supported. Once a bank has been
activated it must be precharged before another Bank
Activate command can be applied to the same bank.
The bank active and precharge times are defined as
t
RAS
and
t
RP
, respectively. The minimum time interval
between successive Bank Activate commands to the
same bank is determined by
t
RC
. The minimum time
interval between Bank Active commands to different
banks is
t
RRD
.
Figure 17
Bank Activate Command Cycle
t
RCD
= 3, AL = 2,
t
RP
= 3,
t
RRD
= 2
Address
NOP
Command
T0
T2
T1
T3
T4
Col. Addr.
Bank A
Row Addr.
Bank B
Col. Addr.
Bank B
Internal RAS-CAS delay tRCDmin.
Bank A to Bank B delay tRRD.
Activate
Bank B
Read A
Posted CAS
Activate
Bank A
Read B
Posted CAS
Read A
Begins
Row Addr.
Bank A
Addr.
Bank A
Precharge
Bank A
NOP
Addr.
Bank B
Precharge
Bank B
Row Addr.
Bank A
Activate
Bank A
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
Tn
Tn+1
Tn+2
Tn+3
ACT
tRAS Row Active Time (Bank A)
additive latency AL=2
CK, CK
tCCD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
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| HYB18T512400BF-3S | 制造商:Qimonda 功能描述: |
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| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
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