參數(shù)資料
型號(hào)： HYB18T512160AF
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁(yè)數(shù)： 81/117頁(yè)
文件大?。?/td> 2102K
代理商： HYB18T512160AF
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)當(dāng)前第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
Data Sheet
81
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.4
Output Buffer Characteristics
Table 31
Symbol
I
OH
I
OL
SSTL_18 Output DC Current Drive
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTL_18
–13.4
13.4
Unit
mA
mA
Note
1)2)
1)
V
DDQ
= 1.7 V;
V
OUT
= 1.42 V. (
V
OUT
–
V
DDQ
) /
I
OH
must be less than 21 Ohm for values of
V
OUT
between
V
DDQ
and
V
DDQ
– 280 mV.
2) The values of
I
OH(dc)
and
I
OL(dc)
are based on the conditions given in
1)
and
3)
. They are used to test drive current capability
to ensure
V
IH.MIN
. plus a noise margin and
V
IL.MAX
minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
3)
V
DDQ
= 1.7 V;
V
OUT
= 280 mV.
V
OUT
/
I
OL
must be less than 21 Ohm for values of
V
OUT
between 0 V and 280 mV.
2)3)
Table 32
Symbol
V
OH
V
OL
V
OTR
SSTL_18 Output AC Test Conditions
Parameter
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
SSTL_18
V
TT
+ 0.603
V
TT
– 0.603
0.5
×
V
DDQ
Unit
V
V
V
Note
1)
1) SSTL_18 test load for
V
OH
and
VOL
is different from the referenced load described in
Chapter 8.1
. The SSTL_18 test load
has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into
V
TT
. The SSTL_18 definition assumes that
±
335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA
×
25 Ohm = 335 mV). With an
additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to
V
TT
, at the ouput
device (13.4 mA
×
45 Ohm = 603 mV).
1)
Table 33
Symbol
—
—
—
OCD Default Characteristics
Description
Output Impedance
Pull-up / Pull down mismatch
Output Impedance step size
for OCD calibration
Output Slew Rate
Min.
12.6
0
0
Nominal
18
—
—
Max.
23.4
4
1.5
Unit
Ohms
Ohms
Ohms
Note
1)2)
1) Absolute Specifications (
T
OPER
;
V
DD
= 1.8 V
±
0.1 V;
V
DDQ = 1.8 V
±
0.1 V), altering OCD from default state no longer
requires DRAM to meet timing, voltage and slew rate specifications on I/O’s.
2) Impedance measurement condition for output source dc current:
V
DDQ
= 1.7 V,
V
OUT
= 1420 mV;
(
V
OUT
–
V
DDQ
) /
I
OH
must be less than 23.4 ohms for values of
V
OUT
between
V
DDQ
and
V
DDQ
– 280 mV. Impedance
measurement condition for output sink dc current:
V
DDQ
= 1.7 V;
V
OUT
= –280 mV;
V
OUT
/
I
OL
must be less than 23.4 Ohms
for values of
V
OUT
between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
±
0.75 Ohms under nominal conditions.
5) Slew Rates according to
Chapter 8.2.1
V
IL(ac)
to
V
IH(ac)
with the load specified in
Figure 72
.
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
from AC to AC. This is verified by design and characterization but not subject to production test.
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in
t
DQSQ
and
t
QHS
specification.
8) DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
1)2)3)
4)
S
OUT
1.5
—
5.0
V / ns
1)5)6)7)8)
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3 512-Mbit DDR2 SDRAM
HYB18T512160AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*