參數(shù)資料
型號: HYB18T512160AF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 35/117頁
文件大?。?/td> 2102K
代理商: HYB18T512160AF
Data Sheet
35
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.11
Extended Mode Register EMR(3)
The Extended Mode Register EMR(3) is reserved for
future use and all bits except BA0 and BA1 must be
programmed to 0 when setting the mode register during
initialization. The EMRS(3) is written by asserting low
on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,
while controlling the state of the address pins.
Table 12
Field
BA2
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010
B
)
Bits
Type
1)
Description
16
reg.addr
Bank Address[2]
Note:BA2 is not available on 256Mbit and 512Mbit components
1) w = write only
0
B
Bank Adress[1]
1
B
BA1
, Bank Address
Bank Adress[0]
1
B
BA0
, Bank Address
Address Bus[13:0]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
BA2
, Bank Address
BA1
15
BA0
14
A
[13:0] w
0
B
A[13:0]
, Address bits
-0"4
"! " ! " ! !
!
!
!
!
!
!
!
!
!
!
!
!
!
REG ADDR
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3 512-Mbit DDR2 SDRAM
HYB18T512160AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
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