參數(shù)資料
型號(hào)： HYB18T512160AF
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 69/117頁
文件大?。?/td> 2102K
代理商： HYB18T512160AF
Data Sheet
69
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Figure 54
Self Refresh Timing
Note:
1. Device must be in the “All banks idle” state before
entering Self Refresh mode.
2.
t
XSRD
(
≥
200
t
CK
) has to be satisfied for a Read or a
Read with Auto-Precharge command.
3. t
XSNR
has to be satisfied for any command except a
Read or a Read with Auto-Precharge command
4. Since CKE is an SSTL input,
V
REF
must be
maintained during Self Refresh.
3.25
Power-Down
Power-down is synchronously entered when CKE is
registered LOW, along with NOP or Deselect
command. CKE is not allowed to go LOW while mode
register or extended mode register command time, or
read or write operation is in progress. CKE is allowed to
go LOW while any other operation such as row
activation, Precharge, Auto-Precharge or Auto-Refresh
is in progress, but power-down
I
DD
specification will not
be applied until finishing those operations.
The DLL should be in a locked state when power-down
is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation. DRAM
design guarantees it’s DLL in a locked state with any
CKE intensive operations as long as DRAM controller
complies with DRAM specifications.
If power-down occurs when all banks are precharged,
this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any
bank, this mode is referred to as Active Power-down.
For Active Power-down two different power saving
modes can be selected within the MRS register,
address bit A12. When A12 is set to LOW this mode is
referred as “standard active power-down mode” and a
fast power-down exit timing defined by the
t
XARD
timing
parameter can be used. When A12 is set to HIGH this
mode is referred as a power saving “l(fā)ow power active
power-down mode”. This mode takes longer to exit
from the power-down mode and the
t
XARDS
timing
parameter has to be satisfied.
Entering power-down deactivates the input and output
buffers, excluding CK, CK, ODT and CKE. Also the DLL
is disabled upon entering Precharge Power-down or
slow exit active power-down, but the DLL is kept
enabled during fast exit active power-down. In power-
down mode, CKE LOW and a stable clock signal must
be maintained at the inputs of the DDR2 SDRAM, and
all other input signals are “Don’t Care”. Power-down
duration is limited by 9 times
t
REFI
of the device.
CK/CK
T1
T3
T2
CK/CK may
be halted
CK/CK must
be stable
CKE
>=tXSRD
>= tXSNR
Tn
Tr
Tm
T5
T4
tRP
tis
tAOFD
CMD
Self Refresh
Entry
NOP
Non-Read
Command
Read
Command
T0
tis
tis
ODT
tCKE
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3 512-Mbit DDR2 SDRAM
HYB18T512160AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
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