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參數(shù)資料
| 型號： | HYB18T512160AF |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 67/117頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512160AF |
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Data Sheet
67
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.23.4
Concurrent Auto-Precharge
DDR2 devices support the “Concurrent Auto-
Precharge” feature. A Read with Auto-Precharge
enabled, or a Write with Auto-Precharge enabled, may
be followed by any command to the other bank, as long
as that command does not interrupt the read or write
data transfer, and all other related limitations (e.g.
contention between Read data and Write data must be
avoided externally and on the internal data bus).
The minimum delay from a Read or Write command
with Auto-Precharge enabled, to a command to a
different bank, is summarized in the Command Delay
Table. As defined, the WL = RL - 1 for DDR2 devices
which allows the command gap and corresponding
data gaps to be minimized.
3.24
Refresh
DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated
in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode.
3.24.1
Auto-Refresh Command
Auto-Refresh is used during normal operation of the
DDR2 SDRAM’s. This command is non persistent, so it
must be issued each time a refresh is required. The
refresh addressing is generated by the internal refresh
controller. This makes the address bits ”don’t care”
during an Auto-Refresh command. The DDR2 SDRAM
requires Auto-Refresh cycles at an average periodic
interval of
t
REFI.MAX
.
When CS, RAS and CAS are held LOW and WE HIGH
at the rising edge of the clock, the chip enters the Auto-
Refresh mode. All banks of the SDRAM must be
precharged and idle for a minimum of the precharge
time (
t
RP
) before the Auto-Refresh Command can be
applied. An internal address counter supplies the
addresses during the refresh cycle. No control of the
external address bus is required once this cycle has
started.
When the refresh cycle has completed, all banks of the
SDRAM will be in the precharged (idle) state. A delay
between the Auto-Refresh Command and the next
Activate Command or subsequent Auto-Refresh
Command must be greater than or equal to the Auto-
Refresh cycle time (
t
RFC
).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of
eight Auto-Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum
absolute interval between any Auto-Refresh command
and the next Auto-Refresh command is 9
×
t
REFI
.
Table 19
From Command To Command (different bank,
non-interrupting command)
WRITE w/AP
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
Read w/AP
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
Command Delay Table
Minimum Delay with Concurrent Auto-
Precharge Support
(CL -1) + (BL/2) +
t
WTR
BL/2
1
BL/2
BL/2 + 2
1
Unit
Note
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
1)
1) This rule only applies to a selective Precharge command to another bank, a Precharge-All command is illegal
1)
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