參數(shù)資料
型號: HYB18T512160AF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 39/117頁
文件大小: 2102K
代理商: HYB18T512160AF
Data Sheet
39
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
sw1
3.13
On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2
components that allows a DRAM to turn on/off termi-
nation resistance for each DQ, DQS, DQS, DM for
×
4
and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the
same pin) and RDQS for
×
8 configuration via the ODT
control pin. DQS and RDQS are only terminated when
enabled by EMR(1).
For
×
16 configuration ODT is applied to each DQ,
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
the ODT control pin. UDQS and LDQS are terminated
only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integrity
of the memory channel by allowing the DRAM
controller to independently turn on/off termination resis-
tance for any or all DRAM devices. The ODT function
can be used for all active and standby modes. ODT is
turned off and not supported in Self-Refresh mode.
EES O
Figure 12
Functional Representation of ODT
Switch sw1, sw2 or sw3 are enabled by the ODT pin.
Selection between sw1, sw2 or sw3 is determined by
“Rtt (nominal)” in EMRS(1) address bits A6 & A2.
Target: Rval1 = Rval2 = Rval3 = 2
×
Rtt
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
DRAM
Input
Buffer
Input
Pin
Rval2
Rval2
sw2
sw2
VDDQ
VSSQ
Rval3
Rval3
sw3
sw3
VDDQ
VSSQ
Rval1
Rval1
sw1
VDDQ
VSSQ
ODT_funct2
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