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| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 42/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
47
04212008-66HT-ZLFE
7.3
Jitter Definition and Clock Jitter Specification
Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. Input clock jitter
specification parameters are applicable to DDR2-667 and DDR2-800.
The following table provides an overview of the terminology.
TABLE 38
Average Clock and Jitter Symbols and Definition
Symbol
Parameter
Description
Units
t
CK.AVG
Average clock period
t
CK.AVG is calculated as the average clock period within any consecutive
200-cycle window:
N=200
ps
t
JIT.PER
Clock-period jitter
t
JIT.PER is defined as the largest deviation of any single tCK from tCK.AVG:
t
JIT.PER = Min/Max of {tCKi – tCK.AVG} where i = 1 to 200
t
JIT.PER defines the single-period jitter when the DLL is already locked.
t
JIT.PER is not guaranteed through final production testing.
ps
t
JIT(PER, LCK)
Clock-period jitter
during DLL-locking
period
t
JIT(PER,LCK) uses the same definition as tJIT.PER, during the DLL-locking
period only.
t
JIT(PER,LCK) is not guaranteed through final production testing.
ps
t
JIT.CC
Cycle-to-cycle clock
period jitter
t
JIT.CC is defined as the absolute difference in clock period between two
consecutive clock cycles:
t
JIT.CC = Max of ABS{tCKi+1 – tCKi}
t
JIT.CC defines the cycle - to - cycle jitter when the DLL is already locked.
t
JIT.CC is not guaranteed through final production testing.
ps
t
JIT(CC, LCK)
Cycle-to-cycle clock
period jitter during
DLL-locking period
t
JIT(CC,LCK) uses the same definition as tJIT.CC during the DLL-locking
period only.
t
JIT(CC,LCK) is not guaranteed through final production testing.
ps
t
ERR.2PER
Cumulative error
across 2 cycles
t
ERR.2PER is defined as the cumulative error across 2 consecutive cycles
from
t
CK.AVG:
n= 2 for
t
ERR(2per)
where i = 1 to 200
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
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