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| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 30/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
36
04212008-66HT-ZLFE
6
Currents Measurement Conditions
This chapter describes the currents measurement conditions.
TABLE 32
I
DD Measurement Conditions
Parameter
Symbol
Note
Operating Current - One bank Active - Precharge
t
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are switching; Databus inputs are switching.
I
DD0
1)2)3)4)5)6)
Operating Current - One bank Active - Read - Precharge
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching;
Databus inputs are switching.
I
DD1
Precharge Power-Down Current
All banks idle; CKE is LOW;
t
CK = tCK(IDD);Other control and address inputs are stable; Data bus inputs
are floating.
I
DD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
I
DD2N
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK = tCK(IDD); Other control and address inputs are stable,
Data bus inputs are floating.
I
DD2Q
Active Power-Down Current
All banks open;
t
CK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs
are floating. MRS A12 bit is set to 0 (Fast Power-down Exit).
I
DD3P(0)
Active Power-Down Current
All banks open;
t
CK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
I
DD3P(1)
Active Standby Current
All banks open;
t
CK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
I
DD3N
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =
t
RAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
I
OUT = 0 mA.
I
DD4R
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =
t
RAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
I
DD4W
Burst Refresh Current
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
I
DD5B
Distributed Refresh Current
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 μs interval, CKE is LOW and CS is HIGH between
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
I
DD5D
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