參數(shù)資料
型號(hào)： HYB18T1G800C4F-3
廠商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 128M X 8 DDR DRAM, 0.45 ns, PBGA60
封裝： GREEN, PLASTIC, TFBGA-60
文件頁(yè)數(shù)： 31/58頁(yè)
文件大?。?/td> 1898K
代理商： HYB18T1G800C4F-3
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
37
04212008-66HT-ZLFE
Detailed
I
DD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect.
I
DD7 : Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum
t
RC.IDD without violating tRRD.IDD and tFAW.IDD using a burst length of 4. Control and
address bus inputs are STABLE during DESELECTs. IOUT = 0 mA.
TABLE 33
Definition for
I
DD
Self-Refresh Current
CKE
≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
I
DD6
Operating Bank Interleave Read Current
1. All banks interleaving reads,
I
OUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK =
t
CK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern: see Detailed IDD7 timings shown below.
I
DD7
1)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V.
2)
I
DD specifications are tested after the device is properly initialized.
3)
I
DD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for
I
DD , see Table 33.
6) Timing parameter minimum and maximum values for
I
DD current measurements are defined in Chapter 7.
Timing Patterns for devices with 1KB page size
DDR2-667: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
DDR2-800: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Timing Patterns for devices with 2KB page size
DDR2-667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
DDR2-800: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
Parameter
Description
LOW
Defined as
V
IN ≤ VIL.AC.MAX
HIGH
Defined as
V
IN ≥ VIH.AC.MIN
STABLE
Defined as inputs are stable at a HIGH or LOW level
FLOATING
Defined as inputs are
V
REF = VDDQ / 2
SWITCHING
Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Parameter
Symbol
Note
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