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| 型號(hào)： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 26/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
32
04212008-66HT-ZLFE
TABLE 28
OCD Default Characteristics
Symbol Description
Min.
Nominal
Max.
Unit
Notes
—
Output Impedance
Ω
1)2)
1)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current:
V
DDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than 23.4
ohms for values of
V
OUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V;
V
OUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV.
—
Pull-up / Pull down mismatch
0
—
4
Ω
1)2)3)
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
—
Output Impedance step size for OCD calibration
0
—
1.5
Ω
4)
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
± 0.75 Ohms under nominal
conditions.
S
OUT
Output Slew Rate
1.5
—
5.0
V / ns
1)5)6)7)
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in
t
DQSQ and tQHS
specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
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