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| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
26
04212008-66HT-ZLFE
TABLE 16
Clock Enable (CKE) Truth Table for Synchronous Transitions
TABLE 17
Data Mask (DM) Truth Table
Current State1)
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
CKE
Command
(N)2)3)RAS, CAS, WE,
CS
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
Action (N)2)
Note4)5)
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
Previous Cycle6)
(N-1)
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
Current Cycle6)
(N)
Power-Down
L
X
Maintain Power-Down
7)8)11)
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements.
8) “X” means “don’t care (including floating around
V
REF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to 1 in EMRS(1)).
L
H
DESELECT or NOP
Power-Down Exit
7)9)10)11)
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11)
t
CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
t
IS + 2 × tCK + tIH.
Self Refresh
L
X
Maintain Self Refresh
8)11)12)
12)
V
REF must be maintained during Self Refresh operation.
L
H
DESELECT or NOP
Self Refresh Exit
9)11)12)13)14)
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the
t
XSNR period. Read
commands may be issued only after
t
XSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry 7)9)10)11)15)
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
All Banks Idle
H
L
DESELECT or NOP
Precharge Power-Down
Entry
H
L
AUTOREFRESH
Self Refresh Entry
7)11)14)16)
16) Self Refresh mode can only be entered from the All Banks Idle state.
Any State other than
listed above
H
Refer to the Command Truth Table
17)
17) Must be a legal command as defined in the Command Truth Table.
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
1) Used to mask write data; provided coincident with the corresponding data.
Write Inhibit
H
X
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