- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224000 > HYB18T1G800C4F-3 (QIMONDA AG) 128M X 8 DDR DRAM, 0.45 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 34/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
4
04212008-66HT-ZLFE
TABLE 1
Performance Table
1.2
Description
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two
CMOS
Synchronous
DRAM
device
containing
1,073,741,824 bits and internally configured as an octal bank
DRAM.
The 1-Gbit device is organized as 32 Mbit
×4 I/O ×8 banks or
16 Mbit
×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17 bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V
± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
QAG Speed Code
–25F
–2.5
–3
–3S
Unit
Note
DRAM Speed Grade
DDR2
–800D
–800E
–667C
–667D
CAS-RCD-RP latencies
5–5–5
6–6–6
4–4–4
5–5–5
t
CK
Max. Clock Frequency
CL3
f
CK3
200
MHz
CL4
f
CK4
266
333
266
MHz
CL5
f
CK5
400
333
MHz
CL6
f
CK6
400
–
MHz
CL7
f
CK7
400
–
MHz
Min. RAS-CAS-Delay
t
RCD
12.5
15
12
15
ns
Min. Row Precharge Time
t
RP
12.5
15
12
15
ns
Min. Row Active Time
t
RAS
40
ns
Min. Row Cycle Time
t
RC
52.5
55
52
55
ns
Precharge-All (8 banks) command
period
t
PREA
15
17.5
15
18
ns
1)2)
1) This
t
PREA value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP + 1 × tCK or tnRP + 1 × nCK, depending on the speed bin,
where
t
nRP = RU{ tRP / tCK(avg) } and tRP is the value for a single bank precharge.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB3165800AJ-40 | 8M X 8 FAST PAGE DRAM, 40 ns, PDSO32 |
| HYB39S64400AT-8 | 16M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| HYC532410-50 | 4M X 32 MULTI DEVICE DRAM CARD, 50 ns, XMA88 |
| HYE18M256320CF-7.5 | 8M X 32 DDR DRAM, 6 ns, PBGA90 |
| HYM564124AR-60 | 1M X 64 EDO DRAM MODULE, DMA168 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。