參數(shù)資料
型號： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 38/172頁
文件大小： 795K
代理商： FW82815
82815 GMCH
R
38
Datasheet
3.2.
PCI Configuration Space Access
The GMCH and the I/O Controller Hub are physically connected via the hub interface. From a
configuration standpoint, the hub interface connecting the GMCH and the I/O Controller Hub is
logically
PCI bus #0
. All devices internal to the GMCH and I/O Controller Hub appear to be on PCI bus #0. The
system primary PCI expansion bus is physically attached to the I/O Controller Hub and, from a
configuration standpoint, appears as a hierarchical PCI bus behind a PCI-to-PCI bridge. The primary PCI
expansion bus connected to the I/O Controller Hub has a programmable PCI Bus number.
Note:
Even though the primary PCI expansion bus is referred to as PCI0 in this document it is not PCI bus #0
from a configuration standpoint.
The GMCH contains three PCI devices within a single physical component. The configuration registers
for Devices 0, 1, and 2 are mapped as devices residing on PCI bus #0.
Device 0: Host-hub interface Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus #0. Physically, Device 0 contains the PCI registers, DRAM registers, and other
GMCH specific registers.
Device 1: AGP Bridge supporting 1X/2X/4X transactions. Logically this appears as a PCI device
residing on PCI bus #0.
Device 2: GMCH internal graphics device. These registers contain the PCI registers for the GMCH
internal graphics device. Logically this appears as a PCI device residing on PCI bus #0.
Note:
A physical PCI bus #0 does not exist. The hub interface and the internal devices in the GMCH and I/O
Controller Hub logically constitute PCI Bus #0 to configuration software.
3.2.1.
PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported
by a mapping mechanism implemented within the GMCH. The PCI specification defines two
mechanisms to access configuration space, Mechanism #1 and Mechanism #2.
The GMCH supports only Mechanism #1
The configuration access mechanism makes use of the CONF_ADDR Register and CONF_DATA
Register. To reference a configuration register a DWord I/O write cycle is used to place a value into
CONF_ADDR that specifies the PCI bus, the device on that bus, the function within the device, and a
specific configuration register of the device function being accessed. CONF_ADDR[31] must be 1 to
enable a configuration cycle. CONF_DATA then becomes a window into the four bytes of configuration
space specified by the contents of CONF_ADDR. Any read or write to CONF_DATA results in the
GMCH translating the CONF_ADDR into the appropriate configuration cycle.
The GMCH is responsible for translating and routing the processor I/O accesses to the CONF_ADDR
and CONF_DATA registers to internal GMCH configuration registers, the internal graphic device, or the
hub interface.
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