參數(shù)資料
型號： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據表參考
文件頁數(shù)： 112/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
112
Datasheet
3.6.19.
INTRLINE—Interrupt Line Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Ch
00h
Read/Write
8 bits
Bit
Descriptions
7:0
Interrupt Connection.
Used to communicate interrupt line routing information. POST software writes
the routing information into this register as it initializes and configures the system. The value in this
register indicates which input of the system interrupt controller that the device’s interrupt pin is
connected.
3.6.20.
INTRPIN—Interrupt Pin Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Dh
01h
Read Only
8 bits
Bit
Descriptions
7:0
Interrupt Pin.
As a single function device, the GMCH specifies INTA# as its interrupt pin.
01h = INTA#.
3.6.21.
MINGNT—Minimum Grant Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
Read Only
8 bits
Bit
Descriptions
7:0
Minimum Grant Value.
The GMCH does not burst as a PCI compliant master. (Default=00h).
3.6.22.
MAXLAT—Maximum Latency Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Fh
00h
Read Only
8 bits
Bit
Descriptions
7:0
Maximum Latency Value.
The GMCH has no specific requirements for how often it needs to access
the PCI bus. (Default=00h).
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