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82815 GMCH
R
32
Datasheet
2.8.
Power Signals
Signal Name
Type
Description
V1.8
Power
Core Power (1.85V)
VDDQ
Power
AGP I/O and Display Cache Buffer Supply Power
VSUS3.3
Power
System Memory Buffer Power (Separate 3.3V power plane for power down modes)
VCCDA
Power
Display Power Signal (Connect to an isolated 1.85V plane with VCCDACA1 and
VCCDACA2)
VCCDACA1
Power
Display Power Signal
VCCBA
Power
AGP/Hub I/F Power (1.85V)
VCCDACA2
Power
Display Power Signal
VCCDPLL
Power
System Memory PLL Power (1.85V)
VSSDA
Power
Display Ground Signal
VSSDACA
Power
Display Ground Signal
VSS
Power
Core Ground
VSSDPLL
Power
System Memory PLL Ground
VSSBA
Power
AGP/Hub I/F Ground
2.9.
Clock Signals
Signal Name
Type
Description
HCLK
I
CMOS
Host Clock Input.
Clock used on the host interface. Externally generated
66/100/133 MHz clock.
SCLK
I
CMOS
System Memory Clock.
Clock used on the output buffers of system memory.
Externally generated 100/133 MHz clock.
LTCLK[1:0]
O
CMOS
Display Cache Transmit Clocks.
LTCLK[1:0] are internally generated display
cache clocks used to clock the input buffers of the SDRAM devices.
LOCLK
O
CMOS
Output Clock.
LOCLK is an internally generated clock used to drive LRCLK.
LRCLK
I
CMOS
Receive Clock.
LRCLK is a display cache clock used to clock the input buffers of
the GMCH.
DCLKREF
I
CMOS
Display Interface Clock.
DCLKREF is a 48 MHz clock generated by an external
clock synthesizer to the GMCH.
HLCLK
I
CMOS
Hub Interface Clock.
66 MHz hub interface clock generated by an external clock
synthesizer.
RESET#
I
Global Reset.
Driven by the I/O Controller Hub when PCIRST# is active.