參數(shù)資料
型號(hào)： DS3141+
廠商： Maxim Integrated Products
文件頁數(shù)： 54/88頁
文件大?。?/td> 0K
描述： IC FRAMER DS3/E3 SNGL 144CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 80mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-TECSBGA（13x13）
包裝： 托盤
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
58 of 88
Bit 7: Receive FIFO Overrun Latched (ROVRL). This latched status bit is set to 1 each time the receive FIFO
overruns. ROVRL is cleared when the host processor writes a 1 to it and is not set again until another overrun
occurs (i.e., the FIFO has been read from and then allowed to fill up again). When ROVRL is set, it can cause a
hardware interrupt to occur if the ROVRIE bit in the HSRIE register and the HDLCIE bit in the MSRIE register are
both set to 1. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Register Name:
HSRIE
Register Description:
HDLC Status Register Interrupt Enable
Register Address:
56h
Bit #
7
6
5
4
3
2
1
0
Name
ROVRIE
RPEIE
RPSIE
RABTIE
RHWMIE
TLWMIE
TUDRIE
TENDIE
Default
0
Bit 0: Transmit Packet-End Interrupt Enable (TENDIE). This bit enables an interrupt if the TENDL bit in the
HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Transmit FIFO Underrun Interrupt Enable (TUDRIE). This bit enables an interrupt if the TUDRL bit in the
HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Transmit FIFO Low Watermark Interrupt Enable (TLWMIE). This bit enables an interrupt if the TLWML bit
in the HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Receive FIFO High Watermark Interrupt Enable (RHWMIE). This bit enables an interrupt if the RHWML bit
in the HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Receive Abort Sequence Detected Interrupt Enable (RABTIE). This bit enables an interrupt if the RABTL
bit in the HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 5: Receive Packet-Start Interrupt Enable (RPSIE). This bit enables an interrupt if the RPSL bit in the HSRL
register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 6: Receive Packet-End Interrupt Enable (RPEIE). This bit enables an interrupt if the RPEL bit in the HSRL
register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 7: Receive FIFO Overrun-Interrupt Enable (ROVRIE). This bit enables an interrupt if the ROVRL bit in the
HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
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DS3141+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS314-1010NR WAF 制造商:ON Semiconductor 功能描述:
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DS31412N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS31415 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock
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