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參數(shù)資料
| 型號： | DS3141+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 51/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3/E3 SNGL 144CSBGA |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 160 |
| 控制器類型： | DS3/E3 調幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 80mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA，CSPBGA |
| 供應商設備封裝： | 144-TECSBGA（13x13） |
| 包裝： | 托盤 |
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
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Register Name:
HCR1
Register Description:
HDLC Control Register 1
Register Address:
50h
Bit #
7
6
5
4
3
2
1
0
Name
RHR
THR
RID
TID
TFS
TZSD
TCRCI
TCRCD
Default
0
Bit 0: Transmit CRC Defeat (TCRCD). When this bit is logic 0, the transmit HDLC controller automatically
calculates and appends the 16-bit CRC to the outgoing HDLC message. When this bit is logic 1, the transmit HDLC
controller does not append the CRC to the outgoing message.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
Bit 1: Transmit CRC Invert (TCRCI). When this bit is logic 0, the transmit HDLC controller generates the CRC
normally. When this bit is logic 1, the transmit HDLC controller inverts all 16 bits of the generated CRC. This bit is
ignored when CRC generation is disabled (TCRCD = 1). This bit is useful in testing HDLC operation.
0 = do not invert the generated CRC (normal operation)
1 = invert the generated CRC
Bit 2: Transmit Zero Stuffer Defeat (TZSD). When this bit is logic 0, the transmit HDLC controller performs zero
stuffing on all data between the opening and closing flags of the HDLC message. When this bit is logic 1, the
transmit HDLC controller does not perform zero stuffing.
0 = enable zero stuffing (normal operation)
1 = disable zero stuffing
Bit 3: Transmit Flag/Idle Select (TFS). This control bit determines whether flags or idle bytes are transmitted
between packets.
0 = 7Eh (flags)
1 = FFh (idle)
Bit 4: Transmit Invert Data (TID). When this bit is logic 1, the entire transmit HDLC data stream (including flags
and CRC checksum) is inverted before being transmitted by the DS3/E3 formatter.
0 = do not invert transmit HDLC data stream (normal operation)
1 = invert transmit HDLC data stream
Bit 5: Receive Invert Data (RID). When this bit is logic 1, the entire receive HDLC data stream (including flags and
CRC checksum) is inverted before processing by the receive HDLC controller.
0 = do not invert receive HDLC data stream (normal operation)
1 = invert receive HDLC data stream
Bit 6: Transmit HDLC Reset (THR). A 0-to-1 transition resets the transmit HDLC controller. A reset flushes the
transmit FIFO and causes the transmit HDLC controller to transmit one FEh abort sequence (seven 1s in a row)
followed by continuous transmission of either 7Eh (flags) or FFh (idle) until the beginning of a new packet (at least
two bytes) is written into the transmit HDLC FIFO.
Bit 7: Receive HDLC Reset (RHR). A 0-to-1 transition resets the receive HDLC controller. A reset flushes the
current contents of the receive FIFO and causes the receive HDLC controller to begin searching for a new
incoming HDLC packet.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS3141+ | 功能描述:網絡控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS314-1010NR WAF | 制造商:ON Semiconductor 功能描述: |
| DS31412 | 功能描述:網絡控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31412N | 功能描述:網絡控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31415 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
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