參數(shù)資料
型號(hào)： DS3141+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 53/88頁(yè)
文件大小： 0K
描述： IC FRAMER DS3/E3 SNGL 144CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 80mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-TECSBGA（13x13）
包裝： 托盤
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
57 of 88
Register Name:
HSRL
Register Description:
HDLC Status Register Latched
Register Address:
55h
Bit #
7
6
5
4
3
2
1
0
Name
ROVRL
RPEL
RPSL
RABTL
RHWML
TLWML
TUDRL
TENDL
Default
—
Note: See Figure 7-7 for details on the interrupt signal flow for the status bits in the HSRL register.
Bit 0: Transmit Packet-End Latched (TENDL). This latched status bit is set to 1 each time the transmit HDLC
controller reads a transmit FIFO byte with the corresponding TMEND bit set or when a FIFO underrun occurs.
TENDL is cleared when the host processor writes a 1 to it. When TENDL is set, it can cause a hardware interrupt
to occur if the TENDIE bit in the HSRIE register and the HDLCIE bit in the MSRIE register are both set to 1. The
interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 1: Transmit FIFO Underrun Latched (TUDRL). This latched status bit is set to 1 each time the transmit FIFO
underruns. TUDRL is cleared when the host processor writes a 1 to it and is not set again until another underrun
occurs (i.e., the FIFO has been written to and then allowed to empty again without the TMEND bit set). When
TUDRL is set, it can cause a hardware interrupt to occur if the TUDRIE bit in the HSRIE register and the HDLCIE
bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the
interrupt-enable bits are cleared.
Bit 2: Transmit FIFO Low Watermark Latched (TLWML). This latched status bit is set to 1 when the TLWM
status bit in the HSR register goes high. TLWML is cleared when the host processor writes a 1 to it and is not set
again until TLWM goes high again. When TLWML is set, it can cause a hardware interrupt to occur if the TLWMIE
bit in the HSRIE register and the HDLCIE bit in the MSRIE register are both set to one. The interrupt is cleared
when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 3: Receive FIFO High Watermark Latched (RHWML). This latched status bit is set to 1 when the RHWM
status bit in the HSR register goes high. RHWML is cleared when the host processor writes a one to it and is not
set again until RHWM goes high again. When RHWML is set, it can cause a hardware interrupt to occur if the
RHWMIE bit in the HSRIE register and the HDLCIE bit in the MSRIE register are both set to 1. The interrupt is
cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 4: Receive Abort Sequence Detected Latched (RABTL). This latched status bit is set to 1 each time the
receive HDLC controller detects an abort sequence (seven or more 1s in a row) during packet reception. If the
receive HDLC is not currently receiving a packet, then receiving an abort sequence does not set this status bit.
RABTL is cleared when the host processor writes a 1 to it and is not set again until another abort is detected (at
least one valid flag must be detected before another abort can be detected). When RABTL is set, it can cause a
hardware interrupt to occur if the RABTIE bit in the HSRIE register and the HDLCIE bit in the MSRIE register are
both set to 1. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 5: Receive Packet-Start Latched (RPSL). This latched status bit is set to 1 each time the receive HDLC
controller detects the start of an HDLC packet. RPSL is cleared when the host processor writes a 1 to it and is not
set again until another start of packet is detected. When RPSL is set, it can cause a hardware interrupt to occur if
the RPSIE bit in the HSRIE register and the HDLCIE bit in the MSRIE register are both set to 1. The interrupt is
cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 6: Receive Packet-End Latched (RPEL). This latched status bit is set to 1 each time the HDLC controller
detects a closing flag during reception of a packet, regardless of whether the packet is valid (CRC correct) or not
(bad CRC, abort sequence detected, packet too small, not an integral number of octets, or an overrun occurred).
RPEL is cleared when the host processor writes a 1 to it and is not set again until another message end is
detected. When RPEL is set, it can cause a hardware interrupt to occur if the RPEIE bit in the HSRIE register and
the HDLCIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or
both of the interrupt-enable bits are cleared.
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