參數(shù)資料
型號： B900J24PXX12I
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 80 MHz, OTHER DSP, PQFP44
文件頁數(shù)： 60/100頁
文件大小： 1547K
代理商： B900J24PXX12I
62
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
5 Software Architecture (continued)
5.3
Reset States
Table 54. Register States After Reset
Register
Bits 15—0
Register
Bits 15—0
Register
Bits 15—0
a0
IOPUCA*
* These registers are shown as upper-case because they are not directly program-accessible. They are accessed indirectly via write
operations to the cbit<a—d> registers.
CCCC CCCC CCCC CCCC
r3
a0l
IOPUCB* CCCC CCCC CCCC CCCC
rb
0000 0000 0000 0000
a1
IOPUCC* CCCC CCCC CCCC CCCC
re
0000 0000 0000 0000
a1l
IOPUCD* XXXX CCCC XXXX CCCC
sbita
0000 0000 PPPP PPPP
alf
00
inc
0000 0000 0000 0000
sbitb
0000 0000 PPPP PPPP
ar0
ins
Reset state for ins in B900 is 0110 0100 0101 0110.
0110 0000 0101 0100
sbitc
0000 0000 PPPP PPPP
ar1
i
sbitd
XXXX 0000 XXXX PPPP
ar2
j
sdx
ar3
jtag
sioc
0000 0000 0000 0000
auc
0000 0000 0000 0000
k
ssic
0100 0000 0000 0000
c0
p
ssid
c1
PC
0000 0000 0000 0000
timer0
0000 0000 0000 0000
c2
pi
SSSS SSSS SSSS SSSS
timer1
0000 0000 0000 0000
cbita
0000 0000
pl
timerc
0000 0000 0000 0000
cbitb
0000 0000
pllc
wdogr
cbitc
0000 0000
pr
x
cbitd
XXXX 0000 XXXX
psw
00
y
chipc
0000 0000 000C 000C
pt
ybase
chipo
CCCC
0CCC CCCC CCCC
r0
yl
clkc
0000 0000 0000 0000
r1
cloop
r2
Bit code: Indicates that this bit:
is unknown on powerup reset and unaffected by all other resets.
0
is set to logic zero by all types of resets.
1
is set to logic one by all types of resets.
C
is not affected by a pin (RSTB) reset or watchdog reset; however, powerup reset and JTAG reset clear
the bit to zero.
P
reflects the value on its corresponding input pin.
S
shadows the program counter (PC).
X
may not be written and is read as zero.
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