參數(shù)資料
型號(hào)： B900J24PXX12I
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 80 MHz, OTHER DSP, PQFP44
文件頁(yè)數(shù)： 41/100頁(yè)
文件大?。?/td> 1547K
代理商： B900J24PXX12I
Lucent Technologies Inc.
45
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.6 F4 BMU Instructions (continued)
s
Barrel Shifter
s
Normalization and Exponent Computation
aD = aS >> IM16
Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle,
2-word.
aD = aS >> arM
Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.
aD = aS >> aS
Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.
aD = aS >>> IM16 Logical right shift by immediate (32-bit, 0s filled in); 2-cycle, 2-word.
aD = aS >>> arM
Logical right shift by arM (32-bit, 0s filled in); 1-cycle.
aD = aS >>> aS
Logical right shift by aS (32-bit, 0s filled in); 2-cycle.
aD = aS << IM16
Arithmetic left shift* by immediate (36-bit, 0s filled in); 2-cycle, 2-word.
* Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-
extended.
aD = aS << arM
Arithmetic left shift* by arM (36-bit, 0s filled in); 1-cycle.
aD = aS << aS
Arithmetic left shift* by aS (36-bit, 0s filled in); 2-cycle.
aD = aS <<< IM16 Logical left shift by immediate (36-bit, 0s filled in); 2-cycle, 2-word.
aD = aS <<< arM
Logical left shift by arM (36-bit, 0s filled in); 1-cycle.
aD = aS <<< aS
Logical left shift by aS (36-bit, 0s filled in); 2-cycle.
aD = exp(aS)
Detect the number of redundant sign bits in accumulator; 1-cycle.
aD = norm (aS, arM)
Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.
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