參數(shù)資料
型號(hào)： B900J24PXX12I
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 80 MHz, OTHER DSP, PQFP44
文件頁(yè)數(shù)： 37/100頁(yè)
文件大小： 1547K
代理商： B900J24PXX12I
Lucent Technologies Inc.
41
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.2 F2 Special Function Instructions
All forms of the special function instructions require
one word of program memory and execute in one
instruction cycle.
The special functions in Table 24 can be executed con-
ditionally, as in:
if CON instruction
and with an event counter
ifc CON instruction
which means:
if CON is true then
c1 = c1 + 1
instruction
c2 = c1
else
c1 = c1 + 1
The preceding special function instructions can be exe-
cuted unconditionally by writing them directly. For
example, a0 = a1.
Table 24. F2 Special Function Instructions
Statement
Meaning
aD = aS >> 1
Arithmetic right shift (sign
preserved) of the 36-bit
accumulators.
aD = aS >> 4
aD = aS >> 8
aD = aS >> 16
aD = aS
Load destination accumulator from
source accumulator.
aD = –aS
2’s complement.
aD = ~aS
1’s complement.
aD = rnd(aS)
Round upper 20 bits of
accumulator.
aDh = aSh + 1 Increment upper half of
accumulator (lower half cleared).
aD = aS + 1
Increment accumulator.
aD = y
Load accumulator with 32-bit y
register value with sign extend.
aD = p
Load accumulator with 32-bit p
register value with sign extend.
aD = aS << 1
Arithmetic left shift (sign not
preserved) of the lower 32 bits of
accumulators (upper 4 bits are
sign-extended from bit 31 at the
completion of the shift).
aD = aS << 4
aD = aS << 8
aD = aS << 16
Table 25. Replacement Table for F2 Special
Function Instructions
Replace
Value
Meaning
aD, aS
a0, a1
One of the
two DAU
accumulators.
CON
mi, pl, eq, ne, gt, le, lvs,
lvc, mvs, mvc, c0ge, c0lt,
c1ge, c1lt, heads, tails,
true, false, npint, njint,
pllon, plloff, slowon,
slowoff, stopclk, rfrsh,
oddp, evenp, mns1,
nmns1
for definitions.
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