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參數(shù)資料
| 型號(hào)： | B900J24PXX12I |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 80 MHz, OTHER DSP, PQFP44 |
| 文件頁(yè)數(shù)： | 45/100頁(yè) |
| 文件大?。?/td> | 1547K |
| 代理商： | B900J24PXX12I |
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Lucent Technologies Inc.
49
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
5 Software Architecture (continued)
5.2
Register Settings
The following tables, listed alphabetically, describe the programmable registers of the B900.
Note: Some tables in this section use the following abbreviations:
X = don’t care
W = write only
Table 36. alf (Standby and Memory Map) Register
Bit
15
14
13—8
7
6
5
4
3—0
Field
AWAIT
LOWPR
Res
NMNS1
MNS1
EVENP
ODDP
Res
Bit
Field
Description
15
AWAIT
Prepare DSP for standby:
0 = normal B900 operation.
1 = B900 enters standby, powerdown mode.
14
LOWPR
Memory map selection:
0 = select memory MAP1.
1 = select memory MAP3.
13—8
Res
Reserved—read as zero, write as zero.
7
NMNS1
Not minus one:
0 = BMU result is minus one in 2’s complement form.
1 = BMU result is not minus one in 2’s complement form.
6
MNS1
Minus one:
0 = BMU result is not minus one in 2’s complement form.
1 = BMU result is minus one in 2’s complement form.
5
EVENP
Even parity:
0 = BMU result has odd parity.
1 = BMU result has even parity.
4
ODDP
Odd parity:
0 = BMU result has even parity.
1 = BMU result has odd parity.
3—0
Res
Reserved—read as zero, write as zero.
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| B-900-M-10 | 制造商:Thomas & Betts 功能描述: |
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| B-900-M-20 | 制造商:Thomas & Betts 功能描述: |
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