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Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Lucent Technologies Inc.
17
4 Hardware Architecture (continued)
4.1
B900 Architectural Overview (continued)
Table 8. B900 Block Diagram Legend
Symbol
Name
BMU
Bit manipulation unit.
BREAKPNT
Four instruction breakpoint registers.
BYPASS
JTAG bypass register.
cbit<a—d>*
* IOPA and IOPD are not available for the 28-pin SOJ package.
Control registers for IOP<A—D>.
chipc
Chip control register—controls miscellaneous functions.
chipo
Chip option register—configures the watchdog timer and other miscellaneous functions.
clkc
Clock control register.
DUAL-PORT RAM
Internal dual-port random-access memory.
ROM
For
FlashDSP 1609F only.
Internal flash read-only memory (IFROM).
HDS
Hardware development system module.
ID
JTAG device identification register.
IDB
Internal data bus.
Input/output port units IOPA, IOPB, IOPC, and IOPD.
iopuc<a—d>
Pull-up/pull-down control register for IOP<A—D>.
JCON
JTAG control register.
jtag
16-bit serial/parallel register.
pllc
Phase-lock loop control register.
ROM
For B900 only.
Internal read-only memory.
Status registers for IOP<A—D>.
sdx
SIO data register.
SIO
Dual-channel serial I/O port.
sioc
SIO control register.
SSI
Synchronous serial interface unit.
ssic
SSI control register.
ssid
SSI data register.
TIMER
Two programmable timer units (TIMER0 and TIMER1).
timer<0—1>
Timer running count registers.
timerc
Timer control register.
TRACE
Program discontinuity trace buffer.
wdogr
Watchdog timer register.
XAB
X space (program space) address bus.
XDB
X space data bus.
YAB
Y space (data space) address bus.
YDB
Y space data bus.