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| 型號： | B900J24PXX12I |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 80 MHz, OTHER DSP, PQFP44 |
| 文件頁數(shù)： | 40/100頁 |
| 文件大?。?/td> | 1547K |
| 代理商： | B900J24PXX12I |
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44
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.5 F3 ALU Instructions
These instructions, shown in Table 29, are imple-
mented in the DSP1600 core. F3 ALU instructions
allow accumulator two-operand operations with either
another accumulator, the p register, or a 16-bit immedi-
ate operand. The result is placed in a destination accu-
mulator that can be independently specified. All
operations are done with the full 36 bits. For the accu-
mulator with accumulator operations, both inputs are
36 bits. For the accumulator high with immediate oper-
ations, the immediate is sign-extended into bits 35:32
and the lower bits, 15:0, are filled with zeros, except for
the AND operation, for which they are filled with ones.
These conventions allow the user to do operations with
32-bit immediates by programming two consecutive
16-bit immediate operations.
5.1.6 F4 BMU Instructions
The bit manipulation unit in the B900 provides a set of
efficient bit manipulation operations on accumulators.
It contains four auxiliary registers, ar<0—3> (arM, M =
0, 1, 2, 3), two alternate accumulators (aa0—aa1),
which can be shuffled with the working set, and four
flags (oddp, evenp, mns1, and nms1). The flags are
testable by conditional instructions and can be read
and written via bits 4—7 of the alf register. The BMU
also sets the LMI, LEQ, LLV, and LMV flags in the psw
register:
LMI = 1 if negative (i.e., bit 35 = 1)
LEQ = 1 if zero (i.e., bits 35—0 are 0)
LLV = 1 if (a) 36-bit overflow, or if (b) illegal shift on field
width/offset condition
LMV = 1 if bits 31—35 are not the same (32-bit over-
flow)
The BMU instructions and cycle times follow. All BMU
instructions require 1 word of program memory unless
otherwise noted.
Table 29. F3 ALU Instructions
Cachable
(1 cycle)
Not Cachable
(2 cycle)
aD = aS + aT
aD = aS – aT
aD = aS & aT
aD = aS | aT
aD = aS ^ aT
aS – aT
aS & aT
aD = aS + p
aD = aS – p
aD = aS & p
aD = aS | p
aD = aS ^ p
aS – p
aS & p
aD = aSh + IM16
aD = aSh – IM16
aD = aSh & IM16
aD = aSh | IM16
aD = aSh ^ IM16
aSh – IM16
aSh & IM16
aD = aSl + IM16
aD = aSl – IM16
aD = aSl & IM16
aD = aSl | IM16
aD = aSl ^ IM16
aSl – IM16
aSl & IM16
Table 30. Replacement Table for F3 ALU
Instructions
Replace
Value
Meaning
aD, aT, aS
a0 or a1
One of the two
accumulators.
IM16
16-bit value Long immediate data:
sign-, zero-, or one-
extended as appropriate.
aSh
a0h or a1h Upper half of the
accumulator.
aSl
a0l or a1I
Lower half of the
accumulator.
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