參數(shù)資料
型號(hào)： B900J24PXX12I
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 80 MHz, OTHER DSP, PQFP44
文件頁(yè)數(shù)： 28/100頁(yè)
文件大?。?/td> 1547K
代理商： B900J24PXX12I
Lucent Technologies Inc.
33
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
4 Hardware Architecture (continued)
4.8
Timers
The B900 contains two timers, TIMER0 and TIMER1.
TIMER0 is composed of three main blocks: the timer
control register, the prescaler, and the timer itself. The
timer control register, timerc (see Table 53 on
page 61), sets up the operational state of the timer and
prescaler. The prescaler is a programmable divider that
can be set to a count of 2 to 65,536. It provides a wide
range of time delay. The timer itself is a 16-bit binary
counter that can be preloaded with any 16-bit number.
If enabled, the timer counts down at the programmed
rate and generates an interrupt upon reaching zero.
If the TIMER0 interrupt is generated (see Table 11 on
page 23), program control jumps to location 0x0004
where typically a branch to an interrupt service routine
should be placed. Writing the timer0 register sets the
initial count into the timer and loads the period register
with the same value for repeated count cycles.
The following functions are programmable in the
timerc register:
s
SELTIMCK
n selects the clock source for the timers.
If zero, the timer counts off of the low-frequency
clock, CLKLOW. If one, the timer counts off of the
free-running clock, CLKFREE.
s
COUNT
n starts TIMERn counting when set.
s
RELOAD
n enables repeated counts of TIMERn
when set. If zero, TIMER
n counts down once and
stops. If one, TIMER
n automatically reloads the pre-
vious starting value from the period register into the
timer
n register, and recommences counting down.
s
PRESCALE
n encodes the value of the divider of the
clock going to the counter. For each timer, it ranges
from CLKTIM
n/2 to CLKTIMn/65,536, where
CLKTIM
n is the clock source for each timer.
The timer interrupt can be individually enabled or dis-
abled through the inc register. The timer can be
stopped and started by software and can be reloaded
with a new delay at any time. Its current value can also
be read by software. When the B900 is reset, the timer
is guaranteed to be in an inactive state.
The timer is normally run with two data move instruc-
tions, one to write the timer0 register with the initial
count, and the second to write the timerc register with
initial values. Setting COUNTEN0 starts the counting
of TIMER0.
When the B900 is reset, the control bits of the timerc
register and the timer itself are initialized to 0. This sets
the prescaler to CLKTIM0/2, turns off the reload fea-
ture, disables timer counting, selects the low-
frequency clock to the timer, and initializes the timer
value to its inactive state. The act of resetting the
device does not cause a timer interrupt. The period
register is not initialized on reset.
TIMER1 is the same as TIMER0 and is automatically
powered down when TIMER
n is not enabled.
4.9
Watchdog Timer
The watchdog timer allows for protection from cata-
strophic loss of control of the B900 by the software sys-
tem. It can be programmed for one of three time-out
intervals. The watchdog timer clock is nominally
32 kHz (selectable as the divided-down input clock—
divided by 128 only—or the internal ring oscillator out-
put).
When the watchdog timer is enabled, it can be pro-
grammed to time-out based on counting out one of
three periods. This time period is the watchdog input
clock period multiplied by 212, 214, or 216. It is specified
by the WDEN[1:0] bits in the chipo register (see
When the watchdog timer is enabled and counting, the
current watchdog count value is not viewable; however,
the timer can be reset at any time by writing any value
to the watchdog reset register, wdogr. If the watchdog
timer ever counts out the specified time between
wdogr writes, it initiates a chip reset and asserts the
RSTB pin low. The fact that a watchdog chip reset has
occurred may be determined by reading the WDRST
bit in the chipc register (see Table 39 on page 51),
which is set after such a reset takes place.
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