參數(shù)資料
型號： ADV7184BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 96/112頁
文件大?。?/td> 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 投影儀，錄音機，安全
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
ADV7184
Rev. A | Page 84 of 112
Table 105 provides a detailed description of the registers located in the user map.
Table 105. User Map Detailed Description
Address
Register
Bit Description
7 6 5 4 3 2 1 0 Comments
Notes
0 0 0 0 CVBS in on AIN1; SCART: G on
AIN6/AIN9, B on AIN4/AIN7,
R on AIN5/AIN8
0 0 0 1 CVBS in on AIN2; SCART: G on
AIN6/AIN9, B on AIN4/AIN7,
R on AIN5/AIN8
0 0 1 0 CVBS in on AIN3; SCART: G on
AIN6/AIN9, B on AIN4/AIN7,
R on AIN5/AIN8
0 0 1 1 CVBS in on AIN4; SCART: G on
AIN9, B on AIN7, R on AIN8
0 1 0 0 CVBS in on AIN5; SCART: G on
AIN9, B on AIN7, R on AIN8
0 1 0 1 CVBS in on AIN6; SCART: G on
AIN9, B on AIN7, R on AIN8
Composite and SCART RGB
(RGB analog input options
selectable via RGB_IP_SEL).
0 1 1 0 Y on AIN1, C on AIN4
0 1 1 1 Y on AIN2, C on AIN5
1 0 0 0 Y on AIN3, C on AIN6
S-video.
1 0 0 1 Y on AIN1, Pb on AIN4, Pr on AIN5
0x00
Input Control
1 0 1 0 Y on AIN2, Pb on AIN3, Pr on AIN6
YPbPr.
1 0 1 1 CVBS in on AIN7; SCART: G on
AIN6, B on AIN4, R on AIN5
1 1 0 0 CVBS in on AIN8; SCART: G on
AIN6, B on AIN4, R on AIN5
1 1 0 1 CVBS in on AIN9; SCART: G on
AIN6, B on AIN4, R on AIN5
1 1 1 0 CVBS in on AIN10; SCART: G on
AIN6/AIN9, B on AIN4/AIN7,
R on AIN5/AIN8
INSEL [3:0]. These bits allow the user to
select an input channel and format.
1 1 1 1 CVBS in on AIN11; SCART: G on
AIN6/AIN9, B on AIN4/AIN7,
R on AIN5/AIN8
Composite and SCART RGB
(RGB analog input options
selectable via RGB_IP_SEL).
0 0 0 0
Autodetect PAL (B/G/H/I/D), NTSC
(without pedestal), SECAM
0 0 0 1
Autodetect PAL (B/G/H/I/D), NTSC M
(with pedestal), SECAM
0 0 1 0
Autodetect PAL N, NTSC M
(without pedestal), SECAM
0 0 1 1
Autodetect PAL N, NTSC M (with
pedestal), SECAM
0 1 0 0
NTSC J
VID_SEL [3:0]. These bits allow the user to
select the input video standard.
0 1 0 1
NTSC M
0 1 1 0
PAL 60
0 1 1 1
NTSC 4.43
1 0 0 0
PAL B/G/H/I/D
1 0 0 1
PAL N (B/G/H/I/D without pedestal)
1 0 1 0
PAL M (without pedestal)
1 0 1 1
PAL M
1 1 0 0
PAL Combination N
1 1 0 1
PAL Combination N
1 1 1 0
SECAM (with pedestal)
1 1 1 1
SECAM (with pedestal)
Reserved.
0 0 0 Set to default
0
Disable vsync processor
ENVSPROC.
1
Enable vsync processor
Reserved.
0
Set to default
0
Standard video input
BETACAM. Enable BETACAM levels. This bit
sets the target value for AGC operation.
1
BETACAM input enable
0
Disable hsync processor
ENHSPLL.
1
Enable hsync processor
0x01
Video Selection
Reserved.
1
Set to default
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