I
參數(shù)資料
型號： ADV7184BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 23/112頁
文件大小： 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
標準包裝： 1
類型： 視頻解碼器
應用： 投影儀，錄音機，安全
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
ADV7184
Rev. A | Page 18 of 112
ADC1
R
ADC0
CVBS
ADC2
G
ADC3
B
FAST BLANK
POSITION
RESOLVER
FAST BLANK
(FB PIN)
I2C
CONTROL
OUTPUT
FORMATTER
YPrPb
SUBPIXEL
BLENDER
SIGNAL
CONDITIONING
CLAMPING AND
DECIMATION
TIMING
EXTRACTION
VIDEO
PROCESSING
SIGNAL
CONDITIONING
CLAMPING AND
DECIMATION
RGB
≥
YPrPb
CONVERSION
05
47
9-
009
Figure 9. Fast Blanking Configuration
Fast Blank Edge Shaping
FB_EDGE_SHAPE [2:0], Address 0xEF [2:0]
To improve the picture transition for high speed fast blank
switching, an edge-shaping mode is available on the ADV7184.
Depending on the format of the RGB inputs, it may be advan-
tageous to apply different levels of edge shaping. The levels are
selected via the FB_EDGE_SHAPE [2:0] bits. Users are advised
to try each of the settings and select the setting that is most
visually pleasing on their system.
Table 13. FB_EDGE_SHAPE [2:0] Function
FB_EDGE_SHAPE [2:0]
Description
000
No edge shaping
001
Level 1 edge shaping
010 (default)
Level 2 edge shaping
011
Level 3 edge shaping
100
Level 4 edge shaping
101 to 111
Not valid
Contrast Reduction
For overlay applications, text can be more readable if the
contrast of the video directly behind the text is reduced. To
enable the definition of a window of reduced contrast behind
inserted text, the signal applied to the FB pin can be interpreted
as a trilevel signal, as shown in Figure 10.
CVBS SOURCE
100%
CVBS SOURCE
50% CONTRAST
RGB SOURCE
100%
SANDCASTLE
054
79
-0
10
Figure 10. Fast Blank Signal Representation with
Contrast Reduction Enabled
Contrast Reduction Enable
CNTR_ENABLE, Address 0xEF [3]
This bit enables the contrast reduction feature and changes the
meaning of the signal applied to the FB pin.
0 (default)—The contrast reduction feature is disabled, and the
fast blank signal is interpreted as a bilevel signal.
1—The contrast reduction feature is enabled, and the fast blank
signal is interpreted as a trilevel signal.
Contrast Mode
CNTR_MODE [1:0], Address 0xF1 [3:2]
The contrast level in the selected contrast reduction box is
selected using the CNTR_MODE [1:0] bits.
Table 14. CNTR_MODE [1:0] Function
CNTR_MODE [1:0]
Description
00 (default)
25%
01
50%
10
75%
11
100%
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