參數(shù)資料
型號(hào)： ADV7184BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/112頁(yè)
文件大?。?/td> 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 投影儀，錄音機(jī)，安全
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
ADV7184
Rev. A | Page 16 of 112
ADC_SW_MAN_EN, Manual Input Muxing Enable,
Address 0xC4 [7]
ADC0_SW [3:0], ADC0 Mux Configuration,
Address 0xC3 [3:0]
ADC1_SW [3:0], ADC1 Mux Configuration,
Address 0xC3 [7:4]
ADC2_SW [3:0], ADC2 Mux Configuration,
Address 0xC4 [3:0]
ADC3_SW [3:0], ADC3 Mux Configuration,
Address 0xF3 [7:4]
XTAL CLOCK INPUT PIN FUNCTIONALITY
XTAL_TTL_SEL, Address 0x13 [2]
The crystal pad is normally part of the crystal oscillator circuit,
powered from a 1.8 V supply. For optimal clock generation, the
slice level of the input buffer of this circuit is at approximately
half the supply voltage, making it incompatible with TLL level
signals.
0 (default)—A crystal is used to generate the ADV7184 clock.
1—An external TTL level clock is supplied. A different input
buffer can be selected that slices at TTL-compatible levels. This
inhibits operation of the crystal oscillator and therefore can
only be used when a clock signal is applied.
28.63636 MHz CRYSTAL OPERATION
EN28XTAL, Address 0x1D [6]
The ADV7184 can operate on two different base crystal
frequencies. Selecting one over the other may be desirable in
systems in which board crosstalk between different components
leads to undesirable interference between video signals. It is
recommended to use a crystal of frequency 28.63636 MHz to clock
the ADV7184.
0 (default)—The crystal frequency is 27 MHz.
1—The crystal frequency is 28.63636 MHz.
ANTIALIASING FILTERS
The ADV7184 has optional antialiasing filters on each of the
four input channels. The filters are designed for SD video with
approximately 6 MHz bandwidth.
A plot of the filter response is shown in Figure 8. The filters
can be individually enabled via I2C under the control of
AA_FILT_EN [3:0].
AA_FILT_EN [0], Address 0xF3 [0]
0 (default)—The filter on Channel 0 is disabled.
1—The filter on Channel 0 is enabled.
AA_FILT_EN [1], Address 0xF3 [1]
0 (default)—The filter on Channel 1 is disabled.
1—The filter on Channel 1 is enabled.
AA_FILT_EN [2], Address 0xF3 [2]
0 (default)—The filter on Channel 2 is disabled.
1—The filter on Channel 2 is enabled.
AA_FILT_EN [3], Address 0xF3 [3]
0 (default)—The filter on Channel 3 is disabled.
1—The filter on Channel 3 is enabled.
1M
1G
05
479
-00
8
FREQUENCY (Hz)
AT
T
E
NUAT
IO
N
(
d
B)
0
–2
–4
–6
–8
–10
–12
–14
–16
–20
–24
–28
–32
–18
–22
–26
–30
–34
–36
–38
–40
–42
–44
–46
–48
–50
10M
100M
–52
RESPONSE OF AA FILTER WITH CALIBRATED CAPACITORS
Figure 8. Frequency Response of Internal ADV7184 Antialiasing Filters
SCART AND FAST BLANKING
The ADV7184 can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART
compatibility and overlay functionality.
This function is available when INSEL [3:0] is set appropriately
(see Table 9). Timing extraction is always performed by the
ADV7184 on the CVBS signal. However, a combination of the
CVBS and RGB inputs can be mixed and output under the
control of the I2C registers and the FB pin.
Four basic modes are supported:
Static Switch Mode. The FB pin is not used. The timing is
extracted from the CVBS signal, and either the CVBS
content or RGB content can be output under the control of
CVBS_RGB_SEL. This mode allows the selection of a full-
screen picture from either source. Overlay is not possible
in static switch mode.
Fixed Alpha Blending. The FB pin is not used. The timing
is extracted from the CVBS signal, and an alpha blended
combination of the video from the CVBS and RGB sources
is output. This alpha blending is applied to the full screen.
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