參數(shù)資料
型號: ADV7184BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 61/112頁
文件大?。?/td> 0K
描述: IC DECODER VID SDTV MULTI 80LQFP
標(biāo)準包裝: 1
類型: 視頻解碼器
應(yīng)用: 投影儀,錄音機,安全
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
ADV7184
Rev. A | Page 52 of 112
05
47
9-
03
4
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
VSYNC BEGIN
PVBEGSIGN
ODD FIELD?
0
1
NO
YES
PVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 34. PAL Vsync Begin
PVENDDELO, PAL Vsync End Delay on Odd Field,
Address 0xE9 [7]
0 (default)—No delay.
1—Delays vsync going low on an odd field by a line relative
to PVEND.
PVENDDELE, PAL Vsync End Delay on Even Field,
Address 0xE9 [6]
0 (default)—No delay.
1—Delays vsync going low on an even field by a line relative
to PVEND.
PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
0 (default)—Delays the end of vsync. Set for user manual
programming.
1—Advances the end of vsync. Not recommended for user
programming.
05
479
-0
35
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC END
PVENDSIGN
ODD FIELD?
0
1
NO
YES
PVENDDELO
VSEHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 35. PAL Vsync End
PVEND [4:0], PAL Vsync End, Address 0xE9 [4:0]
The default value of PVEND is 10100, indicating the PAL vsync
end position.
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
PFTOGDELO, PAL Field Toggle Delay on Odd Field,
Address 0xEA [7]
0 (default)—No delay.
1—Delays the F toggle/transition on an odd field by a line
relative to PFTOG.
PFTOGDELE, PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
0 (default)—No delay.
1 (default)—Delays the F toggle/transition on an even field by a
line relative to PFTOG.
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